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Apparatus and method for electrolytically depositing copper on a semiconductor workpiece 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C25D-005/10
  • C25D-007/12
  • C25D-005/48
  • C25D-003/38
  • C25D-005/02
출원번호 US-0302711 (2002-11-22)
발명자 / 주소
  • Chen, Linlin
  • Taylor, Thomas
출원인 / 주소
  • Semitool, Inc.
대리인 / 주소
    Perkins Coie LLP
인용정보 피인용 횟수 : 76  인용 특허 : 50

초록

A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less

대표청구항

A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less

이 특허에 인용된 특허 (50)

  1. Martin Sylvia, Alkoxylated dimercaptans as copper additives and de-polarizing additives.
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  22. Dubin Valery ; Nogami Takeshi, Method for reducing oxidation of electroplating chamber contacts and improving uniform electroplating of a substrate.
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  48. Shimauchi Hidenori (Takatsuki JPX) Suzuki Keijiro (Tokyo JPX), Tin whisker-free tin or tin alloy plated article and coating technique thereof.
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  50. Shieh Chan-Long (Paradise Valley AZ) Lungo John (Mesa AZ) Lebby Michael S. (Apache Junction AZ), VCSEL with an intergrated heat sink and method of making.

이 특허를 인용한 특허 (76)

  1. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  2. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  3. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  4. Shia, Rebecca; Chen, Jack Tsung-Yu, Conductive lithographic polymer and method of making devices using same.
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  6. Weidman, Timothy W.; Wijekoon, Kapila P.; Zhu, Zhize; Gelatos, Avgerinos V. (Jerry); Khandelwal, Amit; Shanmugasundram, Arulkumar; Yang, Michael X.; Mei, Fang; Moghadam, Farhad K., Contact metallization scheme using a barrier layer over a silicide layer.
  7. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  8. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  9. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.
  10. Farrar,Paul A., Hplasma treatment.
  11. Farrar, Paul A., Integrated circuit and seed layers.
  12. Farrar,Paul A., Integrated circuit and seed layers.
  13. Foster, Sr., Jimmy G.; Kim, Kyu-Hyoun, Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same.
  14. Foster, Sr., Jimmy G.; Kim, Kyu-Hyoun, Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same.
  15. Foster, Sr., Jimmy G.; Kim, Kyu-Hyoun, Integrated circuit die stacks having initially identical dies personalized with switches.
  16. Foster, Sr., Jimmy G.; Kim, Kyu-Hyoun, Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same.
  17. Foster, Sr., Jimmy G.; Kim, Kyu-Hyoun, Integrated circuit die stacks with rotationally symmetric vias.
  18. Foster, Sr., Jimmy G.; Kim, Kyu-Hyoun, Integrated circuit die stacks with translationally compatible vias.
  19. Foster, Sr., Jimmy G.; Kim, Kyu-Hyoun, Integrated circuit die stacks with translationally compatible vias.
  20. Bandholz, Justin P.; Patel, Pravin; Seidel, Peter R., Integrated circuit with inductive bond wires.
  21. Bandholz, Justin P.; Hinkle, Jonathan R.; Patel, Pravin, Integrating capacitors into vias of printed circuit boards.
  22. Hey, Peter; Kwak, Byung-Sung Leo, Method and apparatus to overcome anomalies in copper seed layers and to tune for feature size and aspect ratio.
  23. Lopatin,Sergey; Shanmugasundram,Arulkumar; Lubomirsky,Dmitry; Pancham,Ian A., Method for forming CoWRe alloys by electroless deposition.
  24. Zheng, Bo; Bajaj, Rajeev; Wang, Zhonghui Alex, Method for regulating the electrical power applied to a substrate during an immersion process.
  25. Zheng, Bo; Wang, Hougong; Dixit, Girish; Chen, Fusen, Method of application of electrical biasing to enhance metal deposition.
  26. Ponoth,Shom; Chen,Steven Shyng Tsong; Fitzsimmons,John Anthony; Spooner,Terry Allen, Method of making a semiconductor structure with a plating enhancement layer.
  27. Chong, Chin Hui; Lee, Choon Kuan, Method of manufacturing an interposer.
  28. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  29. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  30. Kirby, Kyle K., Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
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  39. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filing vias in microelectronic devices.
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  44. Collins,Dale W., Microelectronic workpiece for electrochemical deposition processing and methods of manufacturing and using such microelectronic workpieces.
  45. Clark, Douglas; Oliver, Steven D.; Kirby, Kyle K.; Dando, Ross S., Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces.
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  47. Lee, Teck Kheng; Lim, Andrew Chong Pei, Microfeature workpiece substrates having through-substrate vias, and associated methods of formation.
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  54. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
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  64. Wang,You; Chang,Anzhong; Dukovic,John O., Substrate support element for an electrochemical plating cell.
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  73. Cases, Moises; Kim, Tae Hong; Mandrekar, Rohan U.; Sherali, Nusrat I., Through-hole-vias in multi-layer printed circuit boards.
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  75. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
  76. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
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