Carbon-matrix composites, compositions and methods related thereto
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
B22B-027/12
B22B-027/04
D03D-025/00
D03D-015/00
출원번호
US-0916823
(2001-07-26)
발명자
/ 주소
Gaffney, John J.
Loszewski, Raymond C.
출원인 / 주소
Ballard Material Products Inc.
대리인 / 주소
Foley Hoag LLP
인용정보
피인용 횟수 :
27인용 특허 :
28
초록▼
The present invention relates to carbon-matrix composites, such as carbon--carbon composites, and a method for forming them by forming a fabric of fusible and infusible fibers which can be processed and carbonized to form a composite. The methods disclosed herein permit preparation of composites whi
The present invention relates to carbon-matrix composites, such as carbon--carbon composites, and a method for forming them by forming a fabric of fusible and infusible fibers which can be processed and carbonized to form a composite. The methods disclosed herein permit preparation of composites which are particularly thin, uniform, and highly pure. The invention also relates to preprocessed fabrics and precarbonized composites, such as those comprising carbon or oxidized polyacrylonitrile fibers and fusible polyacrylonitrile fibers.
대표청구항▼
The present invention relates to carbon-matrix composites, such as carbon--carbon composites, and a method for forming them by forming a fabric of fusible and infusible fibers which can be processed and carbonized to form a composite. The methods disclosed herein permit preparation of composites whi
The present invention relates to carbon-matrix composites, such as carbon--carbon composites, and a method for forming them by forming a fabric of fusible and infusible fibers which can be processed and carbonized to form a composite. The methods disclosed herein permit preparation of composites which are particularly thin, uniform, and highly pure. The invention also relates to preprocessed fabrics and precarbonized composites, such as those comprising carbon or oxidized polyacrylonitrile fibers and fusible polyacrylonitrile fibers. structure has rounded corners. 18. The method of claim 1, wherein the metal layer is copper. 19. The method of claim 1, wherein the plurality of dummy structures includes the same material as the dielectric layer. 20. The method of claim 1, wherein the plurality of dummy structures includes a metal. 21. A method of electropolishing a metal layer on a semiconductor wafer comprising: forming a dielectric layer on the semiconductor wafer, wherein the dielectric layer is formed with a recessed area and a non-recessed area; forming a plurality of dummy structures within the recessed area, wherein the plurality of dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the dielectric layer; forming a barrier layer to cover the recessed area, the non-recessed area, and the plurality of dummy structures; forming a metal layer to fill the recessed area and cover the non-recessed area and the plurality of dummy structures; electropolishing the metal layer to expose the barrier layer deposited on the non-recessed area; removing the exposed barrier layer at a first rate; and removing the non-recessed area of the dielectric layer at a second rate. 22. The method of claim 21, wherein the exposed barrier layer and the non-recessed area of the dielectric layer have even surfaces after the exposed barrier layer is removed at a first rate and the non-recessed area of the dielectric layer is removed at a second rate. 23. The method of claim 21, wherein the exposed barrier layer protrudes beyond the non-recessed area after the exposed barrier layer is removed at a first rate and the non-recessed area is removed at a second rate. 24. The method of claim 21, wherein the first rate is equal to the second rate. 25. The method of claim 21, wherein the first rate is lower than the second rate. 26. The method of claim 21, further comprising: removing the exposed barrier layer at a third rate; and removing the non-recessed area of the dielectric at a fourth rate. 27. The method of claim 26, wherein the third rate is higher than the fourth rate. 28. The method of claim 27, wherein the fourth rate is zero. 29. The method of claim 26, wherein the fourth rate is higher than the third rate. 30. The method of claim 29, wherein the third rate is zero. 31. The method of claim 26, wherein the first rate is higher than the second rate. 32. The method of claim 26, wherein the exposed barrier layer and the non-recessed area have even surfaces after the exposed barrier layer is removed at a third rate and the non-recessed area is removed at a fourth rate. 33. The method of claim 26, wherein the exposed barrier layer protrudes beyond the non-recessed area after the exposed barrier layer is removed at a third rate and the non-recessed area is removed at a fourth rate. 34. The method of claim 21, wherein each dummy structure in the plurality has a width, wherein the metal layer has a thickness, wherein the thickness is based on the metal layer deposited on the non-recessed area, and wherein a ratio of the width to the thickness is between about 0.1 to about 1. 35. The method of claim 21, wherein dummy structures in the plurality are spaced apart from each other by a distance, wherein the metal layer has a thickness, wherein the thickness is based on the metal layer deposited on the non-recessed area, and wherein a ratio of the distance to the thickness is between about 1 to about 5. 36. The method of claim 21, further comprising depositing a seed layer on the dielectric layer before depositing the metal layer. 37. The method of claim 21, further comprising depositing a cover layer on the semiconductor wafer after electropolishing the metal layer. 38. The method of claim 21, wherein the recessed area is a wide trench configured to form an interconnection when filled with the metal layer. 39. The method of claim 21, wherein the recessed area is a large rectangular stru
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