$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semiconductor device having a chip size package including a passive element 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/00
출원번호 US-0118403 (2002-04-08)
우선권정보 JP-0118242 (2001-04-17)
발명자 / 주소
  • Aoki, Yutaka
출원인 / 주소
  • Casio Computer Co., Ltd., Oki Electric Industry Co., Ltd.
대리인 / 주소
    Frishauf, Holtz, Goodman & Chick, P.C.
인용정보 피인용 횟수 : 101  인용 특허 : 4

초록

A semiconductor device includes a semiconductor substrate on which a circuit element forming region and a plurality of connection pads are formed, a first columnar electrode which is formed on a first connection pad so as to be electrically connected to the first connection pad, a first conductive l

대표청구항

A semiconductor device includes a semiconductor substrate on which a circuit element forming region and a plurality of connection pads are formed, a first columnar electrode which is formed on a first connection pad so as to be electrically connected to the first connection pad, a first conductive l

이 특허에 인용된 특허 (4)

  1. Irfan M. Rahim, Circuit structure including a passive element formed within a grid array substrate and method for making the same.
  2. Saia Richard Joseph ; Durocher Kevin Matthew ; Cole Herbert Stanley, Flexible interconnect film including resistor and capacitor layers.
  3. Staudinger Joseph (Gilbert AZ) Seely Warren L. (Chandler AZ) Patterson Howard W. (Phoenix AZ), Integrated circuit having passive circuit elements.
  4. Wu Andrew L. (Shrewsbury MA), Planar interconnect for integrated circuits.

이 특허를 인용한 특허 (101)

  1. Gaucher,Brian Paul; Liu,Duixian; Pfeiffer,Ullrich Richard Rudolf; Zwick,Thomas Martin, Apparatus and methods for constructing antennas using vias as radiating elements formed in a substrate.
  2. Appelman, Barry, Automatically enabling the forwarding of instant messages.
  3. Appelman, Barry, Automatically enabling the forwarding of instant messages.
  4. Appelman, Barry, Automatically enabling the forwarding of instant messages.
  5. Appelman, Barry, Automatically enabling the forwarding of instant messages.
  6. Appelman, Barry, Automatically enabling the forwarding of instant messages.
  7. Appleman, Barry, Automatically enabling the forwarding of instant messages.
  8. Yang, Hung Ming, CMOS power sensor.
  9. Yang,Hung Ming, CMOS power sensor.
  10. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  11. Lo, Jian-Wen; Chen, Chien-Fan, Chip having a metal pillar structure.
  12. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  14. Kinugasa, Yukihisa; Furusawa, Toshihiro; Kamatani, Yoshiteru; Higashitsutsumi, Yoshihito, Chip size package (CSP).
  15. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  16. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  17. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang; Lo, Hsin-Jung, Chip structure.
  18. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  19. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  20. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  21. Tang, Sao-Hsia; Wang, Ying-Tung, Circuit board surface structure and fabrication method thereof.
  22. Lin, Mou-Shiung; Chou, Chien-Kang; Chen, Ke-Hung, Circuitry component and method for forming the same.
  23. Droz, Francois, Electronic card having an external connector.
  24. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  26. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  27. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  28. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  33. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  34. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  35. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  36. Aigner,Robert; Franosch,Martin; Meckes,Andreas; Oppermann,Klaus Guenter; Strasser,Marc, Method for producing a cover, method for producing a packaged device.
  37. Su, Michael Z.; Refai-Ahmed, Gamal; Black, Bryan, Method of manufacturing and assembling semiconductor chips with offset pads.
  38. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  39. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  40. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  41. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  42. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  43. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  44. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  45. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  46. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  47. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  48. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  49. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  50. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  51. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  52. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  53. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  54. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  55. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  56. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  57. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  58. Lin, Mou-Shiung; Chou, Chien-Kang; Chen, Ke-Hung, Post passivation structure for a semiconductor device and packaging process for same.
  59. Appelman, Barry, Prohibiting mobile forwarding.
  60. Appelman, Barry, Prohibiting mobile forwarding.
  61. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  62. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
  63. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  64. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  65. Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Ching-San; Lin, Mou-Shiung, Semiconductor chip with passivation layer comprising metal interconnect and contact pads.
  66. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  67. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  68. Lo, Jian-Wen; Chen, Chien-Fan, Semiconductor device.
  69. Yakubo, Yuto, Semiconductor device.
  70. Imanaka, Yoshihiko; Akedo, Jun, Semiconductor device and method of producing the same.
  71. Aiba, Yoshitaka; Fujisawa, Tetsuya; Yonoda, Yoshiyuki, Semiconductor device having a high frequency electrode positioned with a via hole.
  72. Aiba, Yoshitaka; Fujisawa, Tetsuya; Yoneda, Yoshiyuki, Semiconductor device having a high frequency external connection electrode positioned within a via hole.
  73. Watanabe,Hiroto; Nakayama,Osamu; Shiratsuchi,Osamu; Daido,Kazuhiko, Semiconductor device having antenna connection electrodes.
  74. Nishiyama, Tomohiro; Tago, Masamoto, Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same.
  75. Nishiyama,Tomohiro; Tago,Masamoto, Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same.
  76. Nishiyama,Tomohiro; Tago,Masamoto, Semiconductor element including a wet prevention film.
  77. Nishiyama,Tomohiro; Tago,Masamoto, Semiconductor element with conductive columnar projection and a semiconductor device with conductive columnar projection.
  78. Mun, Sung-ho; Kang, Sun-won; Baek, Seung-duk, Semiconductor package apparatus.
  79. Wang, Sheng-Ming; Feng, Hsiang-Ming; Kuo, Yen-Hua, Semiconductor package substrates having layered circuit segments, and related methods.
  80. Shih, Meng-Kai; Lee, Chang-Chi, Semiconductor package with integrated metal pillars and manufacturing methods thereof.
  81. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  82. Weng, Cheng-Yi, Stacked semiconductor packages and related methods.
  83. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
  84. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  85. Chen, Tien-Szu; Lee, Chun-Che; Wang, Sheng-Ming, Substrate for semiconductor package and process for manufacturing.
  86. Chen, Tien-Szu; Lee, Chun-Che; Wang, Sheng-Ming, Substrate for semiconductor package and process for manufacturing.
  87. Chen, Tien-Szu; Lee, Chun-Che; Wang, Sheng-Ming, Substrate for semiconductor package and process for manufacturing.
  88. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  89. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  90. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  91. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  92. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  93. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  94. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  95. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  96. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  97. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  98. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  99. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
  100. Shionoiri, Yutaka, Wireless chip.
  101. Shionoiri, Yutaka, Wireless chip.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로