초록 ▼

Screens generated by a host application are reformatted for viewing by applying styles to the host screens in response to recognized components included therein. In particular, a style defines a desired look and layout to be applied to a respective host screen. The styles are applied to the respecti

Screens generated by a host application are reformatted for viewing by applying styles to the host screens in response to recognized components included therein. In particular, a style defines a desired look and layout to be applied to a respective host screen. The styles are applied to the respective host screens based on recognizing components of the host screen at run time. For example, first and second styles can be associated with respective first and second components included in host screens. The first style is applied to the host screen in which the first component is recognized and the second style is applied to the host screen in which the second component is recognized. Accordingly, the application of the first and second styles provide respective first and second reformatted screens.

대표청구항 ▼

Screens generated by a host application are reformatted for viewing by applying styles to the host screens in response to recognized components included therein. In particular, a style defines a desired look and layout to be applied to a respective host screen. The styles are applied to the respecti

Screens generated by a host application are reformatted for viewing by applying styles to the host screens in response to recognized components included therein. In particular, a style defines a desired look and layout to be applied to a respective host screen. The styles are applied to the respective host screens based on recognizing components of the host screen at run time. For example, first and second styles can be associated with respective first and second components included in host screens. The first style is applied to the host screen in which the first component is recognized and the second style is applied to the host screen in which the second component is recognized. Accordingly, the application of the first and second styles provide respective first and second reformatted screens. s a continuation of U.S. Ser. No. 09/357,183 filed Jul. 19, 1999. ction signal; and a signal-supplying circuit for supplying the output signals of the buffer circuits to the control section, wherein the control section selects any key matrix in which at least one key has been pushed, in accordance with the output signals of the buffer circuits, and supplies a selection signal to the analog-to-digital converter section, and the analog-to-digital converter section converts the output voltage of the key matrix to digital data. 6. The circuit according to claim 5, wherein the analog-to-digital converter section comprises: a multiplexer having an output terminal and input terminals for receiving the voltages from the key matrices, and designed to select one of the voltages in accordance with a selection signal supplied from the control section; and an analog-to-digital converter connected to the output terminal of the multiplexer, for converting the voltage applied from the multiplexer, to digital data. 7. The circuit according to claim 5, further comprising: a register for holding the signal supplied from the control section, in the idle mode; and a selector having a first input terminal for receiving an interrupt signal, a second input terminal for receiving an output signal of the logic circuit and an output terminal connected to the interrupt-signal generating circuit, and designed to select the first input terminal or the second input terminal in accordance with a signal output from the register. 8. An interruption control circuit comprising: a group of key matrices, each having keys and designed to generate different voltages when the keys are operated; an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data; a control section designed to deactivate the same in an idle mode, stop operating in the idle mode, and determine, in a normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section; a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to output a second-level signal when the voltage is lower than the threshold voltage; selection circuits connected to output terminals of the buffer circuits, respectively, each for selecting the output signal of the associated buffer circuit in the idle mode; a logic circuit for receiving signals output from the selection circuits and generating a detection signal when the signal output from any one of the buffer circuits changes; an interrupt-signal generating circuit connected to the logic circuit, for generating a signal for releasing the idle mode and supplying the same to the control section when the logic circuit generates the detection signal; and an activating circuit for activating the analog-to-digital converter section in accordance with the detection signal generated by the logic circuit. 9. The circuit according to claim 8, wherein the activating circuit comprises: a holding circuit for holding a trigger signal supplied from the control section; and an auxiliary logic circuit connected to the holding circuit and the logic circuit, for activating the analog-to-digital converter section in accordance with the trigger signal and the detecting signal supplied from the holding circuit and the logic circuit, respectively. 10. The circuit according to claim 8, which further comprises a signal-supplying circuit for supplying the output signals of the buffer circuits to the control section, and in which the control section selects any key matrix in which at least one key has been pushed, in accordance with the output signals of the buffer circuits, supplied through a signal-supplying circuit, supplies a selection signal to the analog-to-digital converter section, and the analog-to-d igital converter section converts the output voltage of the key matrix to digital data. 11. The circuit according to claim 10, wherein the analog-to-digital converter section comprises: a multiplexer having an output terminal and input terminals for receiving the voltages from the key matrices, and designed to select one of the voltages in accordance with a selection signal supplied from the control section; and an analog-to-digital converter connected to the output terminal of the multiplexer, for converting the voltage applied from the multiplexer, to digital data. 12. The circuit according to claim 8, further comprising: a register for holding the signal supplied from the control section, in the idle mode; and a selector having a first input terminal for receiving an interrupt signal, a second input terminal for receiving an output signal of the logic circuit and an output terminal connected to the interrupt-signal generating circuit, and designed to select the first input terminal or the second input terminal in accordance with a signal output from the register. 13. An interruption control circuit comprising: a group of key matrices, each having keys and designed to generate different voltages when the keys are operated; an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data; a control section designed to deactivate the same in an idle mode, stop operating in the idle mode, and determine, in a normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section; a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to output a second-level signal when the voltage is lower than the threshold voltage; a logic circuit for receiving signals output from the buffer circuits and generating a detection signal when the signal output from any one of the buffer circuits changes; an interrupt-signal generating circuit connected to the logic circuit, for generating a signal for releasing the idle mode and supplying the same to the control section when the logic circuit generates the detection signal; and a channel-selecting circuit for receiving the output signals of the buffer circuits, selecting any key matrix in which at least one key has been pushed, and outputting a selection signal, wherein the analog-to-digital converter section converts, to digital data, the voltage applied from the key matrices in accordance with the selection signal. 14. The circuit according to claim 13, further comprising an activating circuit for activating the analog-to-digital converter section in accordance with the detection signal generated by the logic circuit. 15. The circuit according to claim 14, wherein the activating circuit comprises: a holding circuit for holding a trigger signal supplied from the control section; and an auxiliary logic circuit connected to the holding circuit and the logic circuit, for activating the analog-to-digital converter section in accordance with the trigger signal and the detecting signal supplied from the holding circuit and the logic circuit, respectively. 16. The circuit according to claim 13, which further comprises a signal-supplying circuit for supplying the output signals of the buffer circuits to the control section, and in which the control section selects any key matrix in which at least one key has been pushed, in accordance with the output signals of the buffer circuits, supplied through a signal-supplying circuit, supplies a selection signal to the analog-to-digital converter section, and the analog-to-digital converter section converts the output voltage of the key matrix to digital data. 17. The circuit according to claim 16, wherein the analog-t