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Electroless plating bath composition and method of using 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C23C-018/54
  • C23C-018/52
출원번호 US-0025033 (2001-12-19)
발명자 / 주소
  • Chebiam, Ramanan V.
  • Dubin, Valery M.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 48  인용 특허 : 3

초록

The present invention relates to a cobalt electroless plating bath composition and method of using it for microelectronic device fabrication. In one embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices.

대표청구항

1. A process comprising: combining a primary metal and ammonium sulphate in a first solution; mixing tetramethylammonium hydroxide into the first solution to form a second solution; adjusting pH and temperature of the second solution; mixing dimethylamineborane and ammonium hypophosphite into

이 특허에 인용된 특허 (3)

  1. Brusic Vlasta A. ; Marino Jeffrey Robert ; O'Sullivan Eugene John ; Sambucetti Carlos Juan ; Schrott Alejandro Gabriel ; Uzoh Cyprian Emeka, Cobalt-tin alloys and their applications for devices, chip interconnections and packaging.
  2. Itoh Hideya,JPX ; Toyoda Shizuo,JPX ; Senba Tadao,JPX ; Hasegawa Takao,JPX ; Murayama Toshihiro,JPX ; Takahashi Tomoyasu,JPX ; Fujii Kazutaka,JPX, Electrolessly plated nickel/phosphorus/boron system coatings and machine parts utilizing the coatings.
  3. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (48)

  1. Kolics, Artur; Petrov, Nicolai; Ting, Chiu; Ivanov, Igor, Activation-free electroless solution for deposition of cobalt and method for deposition of cobalt capping/passivation layer on copper.
  2. Ivanov, Igor C., Apparatus configurations for affecting movement of fluids within a microelectric topography processing chamber.
  3. Ivanov, Igor C., Barrier layer configurations and methods for processing microelectronic topographies having barrier layers.
  4. Ivanov, Igor C., Barrier layer configurations and methods for processing microelectronic topographies having barrier layers.
  5. Ivanov, Igor C., Barrier layer configurations and methods for processing microelectronic topographies having barrier layers.
  6. Reid, Jonathan D.; Webb, Eric G.; Minshall, Edmund B.; Kepten, Avishai; Stowell, R. Marshall; Mayer, Steven T., Capping before barrier-removal IC fabrication method.
  7. Reid, Jonathan D.; Webb, Eric G.; Minshall, Edmund B.; Kepten, Avishai; Stowell, R. Marshall; Mayer, Steven T., Capping before barrier-removal IC fabrication method.
  8. Reid, Jonathan D.; Webb, Eric G.; Minshall, Edmund B.; Kepten, Avishai; Stowell, R. Marshall; Mayer, Steven T., Capping before barrier-removal IC fabrication method.
  9. Reid, Jonathan D.; Webb, Eric G.; Minshall, Edmund B.; Kepten, Avishai; Stowell, R. Marshall; Mayer, Steven T., Capping before barrier-removal IC fabrication method.
  10. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  11. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  12. Lachey, Carl Joseph; Maurer, Eric Anthony, Components for compressors having electroless coatings on wear surfaces.
  13. Gorer, Alexander; Chiang, Tony; Lang, Chi-I, Concentrated electroless solution for selective deposition of cobalt-based capping/barrier layers.
  14. Weidman, Timothy W.; Wijekoon, Kapila P.; Zhu, Zhize; Gelatos, Avgerinos V. (Jerry); Khandelwal, Amit; Shanmugasundram, Arulkumar; Yang, Michael X.; Mei, Fang; Moghadam, Farhad K., Contact metallization scheme using a barrier layer over a silicide layer.
  15. Hues, Steven M.; Lovejoy, Michael L.; Mathew, Varughese, Controlled electroless plating.
  16. Hues,Steven M.; Lovejoy,Michael L.; Mathew,Varughese, Controlled electroless plating.
  17. Chen, Qingyun; Valverde, Charles; Paneccasio, Vincent; Petrov, Nicolai; Stritch, Daniel; Witt, Christian; Hurtubise, Richard, Defectivity and process control of electroless deposition in microelectronics applications.
  18. Chen, Qingyun; Valverde, Charles; Paneccasio, Vincent; Petrov, Nicolai; Stritch, Daniel; Witt, Christian; Hurtubise, Richard, Defectivity and process control of electroless deposition in microelectronics applications.
  19. Chen, Qingyun; Valverde, Charles; Paneccasio, Vincent; Petrov, Nicolai; Stritch, Daniel; Witt, Christian; Hurtubise, Richard, Defectivity and process control of electroless deposition in microelectronics applications.
  20. Chen,Qingyun; Valverde,Charles; Paneccasio,Vincent; Petrov,Nicolai; Stritch,Daniel; Witt,Christian; Hurtubise,Richard, Defectivity and process control of electroless deposition in microelectronics applications.
  21. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  22. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  23. Kolics, Artur, Electroless deposition solutions and process control.
  24. Klein, Rita J.; Regner, III, Adam J., Electroless plating bath composition and method of use.
  25. Klein, Rita J.; Regner, III, Adam J., Electroless plating bath composition and method of use.
  26. Chowdhury,Shaestagir; Bauer,Matthew R.; Grunes,Jeff; Ozer,Soley, Electroless plating baths for high aspect features.
  27. Koos, Daniel A.; Mayer, Steven T.; Park, Heung L.; Cleary, Timothy Patrick; Mountsier, Thomas, Fabrication of semiconductor interconnect structure.
  28. Mayer, Steven T.; Koos, Daniel A.; Webb, Eric, Fabrication of semiconductor interconnect structure.
  29. Mayer, Steven T.; Koos, Daniel A.; Webb, Eric, Fabrication of semiconductor interconnect structure.
  30. Dubin,Valery M., Integrated circuit with metal layer having carbon nanotubes and methods of making same.
  31. Koos,Daniel A.; Mayer,Steven T.; Park,Heung L.; Cleary,Timothy Patrick; Mountsier,Thomas, Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage.
  32. Lopatin,Sergey; Shanmugasundram,Arulkumar; Lubomirsky,Dmitry; Pancham,Ian A., Method for forming CoWRe alloys by electroless deposition.
  33. Ivanov, Igor C., Method for passivating hardware of a microelectronic topography processing chamber.
  34. Ivanov, Igor C.; Zhang, Weiguo; Kolics, Artur, Method for strengthening adhesion between dielectric layers formed adjacent to metal layers.
  35. Ivanov, Igor C., Method of depositing fluids within a microelectric topography processing chamber.
  36. Mayer, Steven T.; Porter, David W., Modulated metal removal using localized wet etching.
  37. Lopatin,Sergey; Shanmugasundram,Arulkumar; Emami,Ramin; Fang,Hongbin, Pretreatment for electroless deposition.
  38. Lubomirsky, Dmitry; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Kovarsky, Nicolay Y.; Wijekoon, Kapila, Process for electroless copper deposition.
  39. Mayer, Steven T.; Porter, David W., Reduced isotropic etchant material consumption and waste generation.
  40. Mayer, Steven T.; Porter, David W., Reduced isotropic etchant material consumption and waste generation.
  41. Mathew, Varughese; Garcia, Sam S.; Prindle, Christopher M., Semiconductor process and composition for forming a barrier material overlying copper.
  42. Lopatin,Sergey D.; Shanmugasundrum,Arulkumar; Shacham Diamand,Yosef, Silver under-layers for electroless cobalt alloys.
  43. Ivanov, Igor C., Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes.
  44. Ivanov, Igor C., Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes.
  45. Mayer, Steven T.; Rea, Mark L.; Hill, Richard S.; Kepten, Avishai; Stowell, R. Marshall; Webb, Eric G., Topography reduction and control by selective accelerator removal.
  46. Mayer, Steven T.; Webb, Eric G.; Porter, David W., Wet etching methods for copper removal and planarization in semiconductor processing.
  47. Mayer, Steven T.; Webb, Eric; Porter, David W., Wet etching methods for copper removal and planarization in semiconductor processing.
  48. Mayer, Steven T.; Webb, Eric; Porter, David W., Wet etching methods for copper removal and planarization in semiconductor processing.
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