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Self-aligned silicide process for silicon sidewall source and drain contacts 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0836197 (2001-04-18)
발명자 / 주소
  • Cabral, Jr., Cyril
  • Chan, Kevin K.
  • Cohen, Guy Moshe
  • Guarini, Kathryn Wilder
  • Lavoie, Christian
  • Solomon, Paul Michael
  • Zhang, Ying
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Trapp, Esq., Robert M.McGinn & Gibb, PLLC
인용정보 피인용 횟수 : 54  인용 특허 : 12

초록

A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal laye

대표청구항

A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal laye

이 특허에 인용된 특허 (12)

  1. Xiang Qi ; Pramanick Shekhar, Elevated source/drain salicide CMOS technology.
  2. Kepler Nick ; Wieczorek Karsten,DEX ; Wang Larry ; Besser Paul Raymond, Formation of junctions by diffusion from a doped amorphous silicon film during silicidation.
  3. Krivokapic Zoran ; Krishnan Srinath ; Yeap Geoffrey Choh-Fei ; Buynoski Matthew, Method for increasing gate capacitance by using both high and low dielectric gate material.
  4. Cabral ; Jr. Cyril (Ossining NY) Clevenger Lawrence A. (Lagrangeville NY) d\Heurle Francois M. (Ossining NY) Harper James M. E. (Yorktown Heights NY) Mann Randy W. (Jericho VT) Miles Glen L. (Essex J, Method for lowering the phase transformation temperature of a metal silicide.
  5. Solomon Paul Michael ; Wong Hon-Sum Philip, Method for making single and double gate field effect transistors with sidewall source-drain contacts.
  6. Brodsky Stephen Bruce ; Cabral ; Jr. Cyril ; Carruthers Roy Arthur ; Harper James McKell Edwin ; Lavoie Christian ; O'Neil Patricia Ann ; Wang Yun Yu, Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging.
  7. Agnello Paul D. (Wappingers Falls NY) Cabral ; Jr. Cyril (Ossining NY) Clevenger Lawrence A. (LaGrangeville NY) Copel Matthew W. (Yorktown Heights NY) d\Heurle Francois M. (Ossining NY) Hong Qi-Zhong, Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using.
  8. Prabhakar Venkatraman, Process for forming silicon-on-insulator devices using a nitriding agent.
  9. Maa Jer-shen ; Hsu Shen Teng, Raised silicided source/drain electrode formation with reduced substrate silicon consumption.
  10. Ajmera, Atul Champaklal; Cabral, Jr., Cyril; Carruthers, Roy Arthur; Chan, Kevin Kok; Cohen, Guy Moshe; Kozlowski, Paul Michael; Lavoie, Christian; Newbury, Joseph Scott; Roy, Ronnen Andrew, Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby.
  11. Cyril Cabral, Jr. ; Roy Arthur Carruthers ; Kevin K. Chan ; Guy M. Cohen ; Kathryn Wilder Guarini ; James M. Harper ; Christian Lavoie ; Paul M. Solomon, Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices.
  12. Agnello Paul D. (Wappingers Falls NY) Cabral ; Jr. Cyril (Ossining NY) Clevenger Lawrence A. (LaGrangeville NY) Copel Matthew W. (Yorktown Heights NY) d\Heurle Francois M. (Ossining NY) Hong Qi-Zong , Thin film for a multilayer semiconductor device for improving thermal stability and a method thereof.

이 특허를 인용한 특허 (54)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  4. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  5. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  6. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  18. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  19. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  20. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  21. Yates, Colin D.; Neville, Christopher L., Method of aligning deposited nanotubes onto an etched feature using a spacer.
  22. Yates, Colin D.; Neville, Christopher L.; Rueckes, Thomas; Konsek, Steven L.; Meinhold, Mitchell; Bertin, Claude L., Method of aligning deposited nanotubes onto an etched feature using a spacer.
  23. Yates, Colin D.; Rueckes, Thomas; Konsek, Steven L.; Meinhold, Mitchell; Bertin, Claude L., Method of aligning nanotubes and wires with an etched feature.
  24. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  25. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  26. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  27. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  28. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  29. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  30. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  31. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  32. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  33. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  34. Ganguli, Seshadri; Yu, Sang-Ho; Phan, See-Eng; Chang, Mei; Khandelwal, Amit; Ha, Hyoung-Chan, Process for forming cobalt and cobalt silicide materials in tungsten contact applications.
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  36. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  37. Mathew,Varughese; Mathew,Leo, Semiconductor device having conductive spacers in sidewall regions and method for forming.
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  42. McKinnell, James C.; Chen, Chien-Hua; Diest, Kenneth; Kramer, Kenneth M.; Kearl, Daniel A., Semiconductor package with getter formed over an irregular structure.
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  44. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  45. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  46. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  47. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  48. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  49. Clevenger, Lawrence A.; Dalton, Timothy J.; Hsu, Louis C.; Radens, Carl; Wong, Kwong Hon; Yang, Chih Chao, Structure and method for MOSFET gate electrode landing pad.
  50. Clevenger, Lawrence A.; Dalton, Timothy J.; Hsu, Louis C.; Radens, Carl; Wong, Kwong Hon; Yang, Chih-Chao, Structure and method for MOSFET gate electrode landing pad.
  51. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  52. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  53. Doris,Bruce B.; Ieong,Meikei; Ren,Zhibin; Solomon,Paul M.; Yang,Min, Ultra thin body fully-depleted SOI MOSFETs.
  54. Doris,Bruce B.; Ieong,Meikei; Ren,Zhibin; Solomon,Paul M.; Yang,Min, Ultra thin body fully-depleted SOI MOSFETs.
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