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Method for forming Co-W-P-Au films 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0966629 (2001-09-27)
발명자 / 주소
  • Sambucetti, Carlos Juan
  • Rubino, Judith Marie
  • Edelstein, Daniel Charles
  • Cabral, Jr., Cyryl
  • Walker, George Frederick
  • Gaudiello, John G
  • Wildman, Horatio Seymour
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Trepp, Robert M.Tung, Randy W.
인용정보 피인용 횟수 : 17  인용 특허 : 18

초록

A method for forming a quaternary alloy film of Co--W--P--Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated

대표청구항

1. An alloy film comprising: a Co--W--P film layer, and a Au layer on top of said Co--W--P film layer with Au atoms diffused into said Co--W--P film layer forming a Co--W--P--Au alloy film, said Au layer having a thickness between about 200 .ANG. and about 2000 .ANG.. 2. An alloy film accordin

이 특허에 인용된 특허 (18)

  1. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
  2. Bin Zhao ; Liming Tsau, Dual-damascene interconnect structures and methods of fabricating same.
  3. Djokic Stojan,CAX ITX T5X 5H1 ; Lepard Ross,CAX ITX T8L 4B9 ; Roy Robert,CAX ITX T6H 4A2, Electroless/electrolytic methods for the preparation of metallized ceramic substrates.
  4. Ushio Jiro (Yokohama JPX) Miyazawa Osamu (Yokosuka JPX) Tomizawa Akira (Yokohama JPX) Yokono Hitoshi (Ibaraki JPX) Kanda Naoya (Yokohama JPX) Matsuura Naoko (Yokohama JPX) Ando Setsuo (Kawasaki JPX) , Electronic device plated with gold by means of an electroless gold plating solution.
  5. Alexander Guy B. (Salt Lake City UT) Nadkarni Ravindra M. (Wrentham MA), Method for electroless plating of ultrafine or colloidal particles and products produced thereby.
  6. Lin Kwang-Lung (Tainan TWX) Lee Chwan-Ying (Tainan TWX), Method for producing electroless barrier layer and solder bump on chip.
  7. Baigetsu Aiichirou (Kyoto JPX), Method of forming conductor lines of a semiconductor device.
  8. Allred David (Troy MI) Dec Krystyna (Troy MI) Jackett Nancy (Westland MI) Van Nguyen On (Sterling Heights MI) Reyes Jaime (Birmingham MI), Method of manufacturing a thermoelectric element.
  9. Lopatin Sergey ; Nogami Takeshi ; Pramanik Shekhar, Method of metal/polysilicon gate formation in a field effect transistor.
  10. Nomura Takuji (Otsu JPX) Watanabe Hiroshi (Sagamihara JPX), Method of plating a bonded magnet and a bonded magnet carrying a metal coating.
  11. Berman Elliot (Los Angeles CA), Photoconductive device coontaining electroless metal deposited conductive layer.
  12. Krulik Gerald A. (Lake Forest CA) Mandich Nenad V. (Homewood IL) Singh Rajwant (Fullerton CA), Plating rate improvement for electroless silver and gold plating.
  13. Tamaki Masanori (Gifu JPX), Printed circuit boards.
  14. Uzoh Cyprian E., Process for forming a copper-containing film.
  15. Pine Lloyd A. (Greenwell Springs LA), Redispersion of noble metals on supported catalysts.
  16. De Bruin Leendert (Eindhoven NLX) Verhaar Robertus D. J. (Eindhoven NLX) Van Laarhoven Josephus M. F. G. (Eindhoven NLX), Selectively plating conductive pillars in manufacturing a semiconductor device.
  17. Hupe Jrgen (Langenfeld DEX) Kronenberg Walter (Cologne DEX), Through-hole plate printed circuit board with resist and process for manufacturing same.
  18. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (17)

  1. Weiner, Kurt H.; Chiang, Tony P.; Francis, Aaron; Schmidt, John, Advanced mixing system for integrated tool having site-isolated reactors.
  2. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  3. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  4. Chen, Qingyun; Valverde, Charles; Paneccasio, Vincent; Petrov, Nicolai; Stritch, Daniel; Witt, Christian; Hurtubise, Richard, Defectivity and process control of electroless deposition in microelectronics applications.
  5. Lazovsky, David E.; Malhotra, Sandra G.; Boussie, Thomas R., Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region.
  6. Lazovsky, David E.; Malhotra, Sandra G.; Boussie, Thomas R., Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region.
  7. Lazovsky,David E.; Malhotra,Sandra G.; Boussie,Thomas R., Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region.
  8. Li, Shijian; Kolics, Artur K.; Arunagiri, Tiruchirapalli N., Methods and solutions for preventing the formation of metal particulate defect matter upon a substrate after a plating process.
  9. Chiang, Tony P.; Lazovsky, David E.; Boussie, Thomas R.; Gorer, Alexander, Methods for discretized processing of regions of a substrate.
  10. Lazovsky,David E.; Chiang,Tony P.; Keshavarz,Majid, Molecular self-assembly in substrate processing.
  11. Dai, Haixia; Pakbaz, Khashayar; Spaid, Michael; Nikiforov, Theo, Plating bath and surface treatment compositions for thin film deposition.
  12. Chiang, Tony P.; Lazovsky, David E.; Malhotra, Sandra G., Processing substrates using site-isolated processing.
  13. Dai, Haixia; Pakbaz, Khashayar; Spaid, Michael; Nikiforov, Theo, Seed layers, cap layers, and thin films and methods of making thereof.
  14. Faust,Richard A.; Park,Young Joon, Selectively encased surface metal structures in a semiconductor device.
  15. Fresco, Zachary; Lang, Chi-I; Malhotra, Sandra G.; Chiang, Tony P.; Boussie, Thomas R.; Kumar, Nitin; Tong, Jinhong; Duong, Anh, Substrate processing including a masking layer.
  16. Weiner, Kurt H.; Chiang, Tony P.; Pinto, Gustavo A., System and method for increasing productivity of combinatorial screening.
  17. Chiang, Tony P.; Lazovsky, David E.; Boussie, Thomas R.; McWaid, Thomas H.; Gorer, Alexander, Systems for discretized processing of regions of a substrate.
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