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A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thic

A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal.

대표청구항 ▼

A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thic

A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal. unneling for Data Read-Out, " pp. 136-140. IBM Technical Disclosure Bulletin, vol. 32, No. 8A, Jan. 1990, "Optimal Growth Technique and Structure for Strain Relaxation of Si-Ge Layers on Si Substrates", pp. 330-331. Ishikawa et al., "Creation of Si-Ge-based SIMOX structures by low energy oxygen implantation," Proceedings 1997 IEEE International SOI Conference (Oct. 1997) pp. 16-17. Ishikawa et al., "SiGe-on-insulator substrate using SiGe alloy grown Si(001)," Applied Physics Letters, vol. 75, No. 7 (Aug. 16, 1999) pp. 983-985. Ismail, "Si/SiGe High-Speed Field-Effect Transistors," Electron Devices Meeting, Washington, D.C. (Dec. 10, 1995) pp. 20.1.1-20.1.4. Kim et al., "A Fully Integrated 1.9-GHz CMOS Low-Noise Amplifier", IEEE Microwave and Guided Wave Letters, vol. 8, No. 8, Aug. 1998, pp. 293-295. Kuznetsov et al., "Technology for high-performance n-channel SiGe modulation-doped field-effect transistors," J. Vac. Sci. Technol., B 13(6), pp. 2892-2896 (Nov./Dec. 1995). Larson, "Integrated Circuit Technology Options for RFIC's□Present Status and Future Directions", IEEE Journal of Solid-State Circuits, vol. 33, No. 3, Mar. 1998, pp. 387-399. Lee and Wong, "CMOS RF Integrated Circuits at 5 GHz and Beyond", Proceedings of the IEEE, vol. 88, No. 10, Oct. 2000, pp. 1560-1571. Lu et al., "High Performance 0.1 □m Gate-Length P-Type SiGe MODFET's and MOS-MODFET's ", IEEE Transactions on Electron Devices, vol. 47, No. 8, Aug. 2000, pp. 1645-1652. M. Kummer et al., "Low energy plasma enhanced chemical vapor deposition," Materials Science and Engineering B89 (2002) pp. 288-295. Maszara, "Silicon-On-Insulator by Wafer Bonding: A Review," Journal of the Electrochemical Society, No. 1, (Jan. 1991) pp. 341-347. Mizuno et al., "Electron and Hold Mobility Enhancement in Strained-Si MOSFET's on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology," IEEE Electron Device Letters, vol. 21, No. 5 (May 2000) pp. 230-232. Mizuno et al., "High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology," IEEE IDEM Technical Digest, (1999 International Electron Device Meeting) pp. 934-936. Nayak et al., "High-Mobility Strained-Si PMOSFET's "; IEEE Transactions on Electron Devices, vol. 43, No. 10, Oct. 1996, pp. 1709-1716. Papananos, "Radio-Frequency Microelectronic Circuits for Telecommunication Applications", Kluwer Academic Publishers, 1999, pp. 115-117, 188-193. Rim et al., "Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs"; IEDM, 1995, pp.