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A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under bump metall

A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under bump metallurgy layer. In one embodiment, the removal of a cap layer which insulates the contact pad area and the deposition of the under bump metallurgy layer are carried out without leaving a vacuum environment.

대표청구항 ▼

A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under bump metall

A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under bump metallurgy layer. In one embodiment, the removal of a cap layer which insulates the contact pad area and the deposition of the under bump metallurgy layer are carried out without leaving a vacuum environment. thin layers of dielectric; a passivation layer over said fine line metallization system; a thick, wide metallization system formed above said passivation layer, wherein said thick, wide metallization system is used as a distribution network for an electrical stimulus, and wherein said thick, wide metallization system is connected to said one or more ESD circuits, said one or more internal circuits, and to at least one off-chip contact pin; and at least one wire-bondable bond pad created over the surface of said thick layers of dielectric, said at least one wire-bondable bond pad being connected with said thick, wide metallization system. 2. The interconnect structure of claim 1 wherein said distribution network is connected to said ESD circuits and to said one or more internal circuits by vias, which are formed through said passivation layer, and through said one or more thin layers of dielectric. 3. The interconnect structure of claim 2 wherein said electrical stimulus comprises a power or ground voltage. 4. The interconnect structure of claim 3 wherein said ESD circuit is connected in parallel with said one or more internal circuits, through said distribution network. 5. The interconnect structure of claim 3 wherein said distribution network acts as a global distribution for said power or ground voltages, and said vias are further connected to local power/ground distribution networks formed in said fine line metallization system. 6. The interconnect structure of claim 2 wherein said electrical stimulus comprises a clock or signal voltage. 7. The interconnect structure of claim 6, further comprising driver, receiver or I/O circuits connected in series between said one or more off-chip contact pins and said distribution network. 8. The interconnect structure of claim 7 wherein said ESD circuit is connected in parallel with said driver, receiver or I/O circuits. 9. The interconnect structure of claim 6 wherein said distribution network acts as a global distribution for said clock or signal voltages, and said vias are further connected to local clock/signal distribution networks formed in said fine line metallization system. 10. The interconnect structure of claim 6 wherein said distribution network acts as a global distribution for said clock or signal voltages, and said vias are further connected to local clock/signal distribution networks formed in said fine line metallization system. 11. The interconnect structure of claim 1 wherein metal in said thick, wide metallization system is greater than about 1 micrometer in thickness. 12. The interconnect structure of claim 1 wherein said one or more thick layers of dielectric are each greater than about 2 micrometers in thickness. 13. A method of forming post passivation interconnect structure, comprising: providing one or more internal circuits comprising one or more active devices formed in and on a semiconductor substrate; providing one or more ESD circuits formed in and on said semiconductor substrate; providing a fine line metallization system, formed over said semiconductor substrate in one or more thin layers of dielectric; providing a passivation layer over said fine line metallization system; providing a thick, wide metallization system formed above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for an electrical stimulus, and wherein said thick, wide metallization system is connected to said one or more ESD circuits, said one or more internal circuits, and to at least one off-chip contact pin; and providing at least one wire-bondable bond pad over said thick layers of dielectric, said at least one wire-bondable bond pad being connected with said thick, wide metallization system. 14. The method of claim 13 wherein said distribution network is connected to said ESD circuit