IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0897906
(2001-07-05)
|
우선권정보 |
JP-0202235 (2000-07-04); JP-0202726 (2000-07-04); JP-0212979 (2000-07-13); JP-0213084 (2000-07-13); JP-0202235 (2001-07-04) |
발명자
/ 주소 |
- Yuasa, Eriko
- Yamakawa, Shuji
- Kato, Shinshu
|
출원인 / 주소 |
- Sumitomo Wiring Systems, Ltd.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
3 인용 특허 :
6 |
초록
▼
An electrical connection box is provided for a vehicle which has a low-voltage battery of maximum output voltage selected from 14V and 28V, and a high-voltage battery of output voltage higher than that of said first battery structure. The electrical connection box has an insulation plate and, fixed
An electrical connection box is provided for a vehicle which has a low-voltage battery of maximum output voltage selected from 14V and 28V, and a high-voltage battery of output voltage higher than that of said first battery structure. The electrical connection box has an insulation plate and, fixed on one face of said insulation plate, first bus bars connected in use to the first battery and second bus bars connected in use to the second battery so that the first and second bus bars are at different potentials. In order to reduce a risk of electrical leakage paths on the insulation plate, at least one of the following features is present: (i) the first bus bars and the second bus bars are separated on the face of the insulation plate by an air insulation zone of width in the range of from about 1 mm to about 30 mm, (ii) an insulation wall stands up on the insulation plate between the first bus bars and the second bus bars, (iii) the second bus bars are embedded in the insulating material.
대표청구항
▼
An electrical connection box is provided for a vehicle which has a low-voltage battery of maximum output voltage selected from 14V and 28V, and a high-voltage battery of output voltage higher than that of said first battery structure. The electrical connection box has an insulation plate and, fixed
An electrical connection box is provided for a vehicle which has a low-voltage battery of maximum output voltage selected from 14V and 28V, and a high-voltage battery of output voltage higher than that of said first battery structure. The electrical connection box has an insulation plate and, fixed on one face of said insulation plate, first bus bars connected in use to the first battery and second bus bars connected in use to the second battery so that the first and second bus bars are at different potentials. In order to reduce a risk of electrical leakage paths on the insulation plate, at least one of the following features is present: (i) the first bus bars and the second bus bars are separated on the face of the insulation plate by an air insulation zone of width in the range of from about 1 mm to about 30 mm, (ii) an insulation wall stands up on the insulation plate between the first bus bars and the second bus bars, (iii) the second bus bars are embedded in the insulating material. regulator. 11. The emergency power supply as claimed in claim 10, wherein the voltage level selector is formed by multiple diodes and a manual operated switch. Y direction of said third group of bump electrodes arranged in the second area, which is enclosed by edges, which are parallel to a diagonal line of said chip and said Y direction, is specified as Sy2, and said fourth group of bump electrodes arranged in said first area is constructed with an array interval distance Sx1 in said X direction in a single line, or said fourth group of bump electrodes arranged in said second area is constructed with an array interval distance Sy1 in said Y direction in a single line. 3. A semiconductor device comprising: a plurality of bump electrodes for external connection arrayed two-dimensionally on the surface of a semiconductor chip where the desired elements and wiring are formed and its appearance is rectangular or square, comprising the first group of bump electrodes including the first bump electrodes as the only means for power supply for allowing the chip operate, the second group of bump electrodes arrayed at the outer periphery of the first group of bump electrodes, and the third group of bump electrodes arrayed at the outer periphery of the second group of bump electrodes, wherein when the direction of two edges orthogonal to each other of said chip are specified as X and Y directions, said first group of bump electrodes and said second group of bump electrodes are arrayed like a grid with an array interval distance Sx1 in said X direction and an array interval distance Sy1 in said Y direction, and said third group of bump electrodes has a structure satisfying Sx2>Sx1 and Sy2>Sy1, when an array interval distance in said X direction of said third group of bump electrodes arranged in the first area, which is enclosed by edges, which are parallel to a diagonal line of said chip and said X direction, is specified as Sx2, and an array interval distance in said Y direction of said third group of bump electrodes arranged in the second area, which is enclosed by edges, which are parallel to a diagonal line of said chip and said Y direction, is specified as Sy2. 4. The semiconductor device mentioned in claim 1 or 2, wherein said first group of bump electrodes include the first bump electrodes as the only means for power supply for allowing said chip operate. 5. The semiconductor device mentioned in claim 2 or 3, wherein said third group of bump electrodes arranged in said first area is arrayed like a grid with an array interval distance Sy1 in said Y direction, or said third group of bump electrodes arranged in said second area is arrayed like a grid with an array interval distance Sx1 in said X direction. 6. The semiconductor device mentioned in claim 2 or 3, wherein said third group of bump electrodes arranged in said first area is arrayed like a staggered grid with an array interval distance Sx1 in said X direction and an array interval distance Sy1 in said Y direction, or said third group of bump electrodes arranged in said second area is arrayed like a staggered grid with an array interval distance Sx1 in said X direction and an array interval distance Sy1 in said Y direction. 7. The semiconductor device mentioned in any of claim 1, 2, or 3, wherein all signal bump electrodes, which input/output signals to/from said chip are included in either said second group of bump electrodes or said third group of bump electrodes. 8. The semiconductor device mentioned in claim 3, wherein said fourth group of bump electrodes are all second power supply bump electrodes for allowing the input/output buffer circuitry of said chip operate. 9. The semiconductor device mentioned in claim 1 or 3, wherein one line from the innermost periphery of said third group of bump electrodes are all second power supply bump electrodes for allowing the input/output buffer circuitry of said chip operate. 10. The semiconductor device mentioned in claim 1 or 3, wherein the first two rows from the outermost periphery of said third group of bump electrodes are all second power supply bump electrodes for allowi ng the input/output buffer circuitry of said chip operate. 11. A semiconductor device comprising: a plurality of external connect terminals arrayed two-dimensionally on the main one surface of a package where a semiconductor is mounted and its appearance is rectangular or square, wherein when the direction of two edges orthogonal to each other of said main one surface are specified as X and Y directions, all of said external connect terminals are arranged at either of the grid points determined with a distance Sx1 between grids in said X direction and a distance Sy1 between grids in said Y direction, and said external connect terminals include a first group of external connect terminals, a second group of external connect terminals arrayed at the outer periphery of the first group of external connect terminals, and a third group of external connect terminals arrayed at the outer periphery of the second group of external connect terminals, wherein said first group of external connect terminals and said second group of external connect terminals are arrayed like a grid with an array interval distance Sx1 in said X direction and an array interval distance Sy1 in said Y direction, and said third group of external connect terminals has a structure satisfying Sx2>Sx1 and Sy2>Sy1, when an array interval distance in said X direction of said third group of external connect terminals arranged in the first area, which is enclosed by edges, which are parallel to a diagonal line of said main one surface and said X direction, is specified as Sx2, and an array interval distance in said Y direction of said third group of external connect terminals arranged in the second area, which is enclosed by edges, which are parallel to a diagonal line of said main one surface and said Y direction, is specified as Sy2. 12. The semiconductor device mentioned in claim 11, wherein said first group of external connect terminals include a group of external connect terminals as the only means for power supply, which allow said chip operate. 13. A semiconductor device comprising: a group of bump-shaped external connect terminals, including a first group of external connect terminals including a first external connect terminals as the only means for power supply for allowing said chip operate, a second group of external connect terminals arrayed at the outer periphery of the first group of external connect terminals, and a third group of external connect terminals arrayed at the outer periphery of the second group of external connect terminals on main one surface of a package on which a semiconductor is mounted and its appearance is rectangular or square, wherein when the direction of two edges orthogonal to each other of said main one surface where the group of external connect terminals are formed are specified as X and Y directions, said first group of external connect terminals and said second group of external connect terminals are arrayed like a grid with an array interval distance Sx1 in said X direction and an array interval distance Sy1 in said Y direction, and said third group of external connect terminals has a structure satisfying Sx2>Sx1 and Sy2>Sy1, when an array interval distance in said X direction of said third group of external connect terminals arranged in the first area, which is enclosed with edges, which are parallel to a diagonal line of said main one surface and said X direction, is specified as Sx2, and an array interval distance in said Y direction of said third group of external connect terminals arranged in the second area, which is enclosed with edges, which are parallel to a diagonal line of the surface where said external connect terminals are formed and said Y direction, is specified as Sy2. 14. The semiconductor device mentioned in claim 13, wherein said third group of external connect terminals arranged in said first area is arrayed like a grid with an array interval distance Sx1 in said X direction and a
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