IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0151157
(2002-05-21)
|
우선권정보 |
JP-0151999 (2001-05-22) |
발명자
/ 주소 |
|
출원인 / 주소 |
- Oki Electric Industry Co., Ltd.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
6 인용 특허 :
3 |
초록
▼
An off-leak current cancel circuit includes an input protection circuit having a first protection transistor connected between a terminal and a high power potential, and a second protection transistor connected between the terminal and a low power potential. The first and second protection transisto
An off-leak current cancel circuit includes an input protection circuit having a first protection transistor connected between a terminal and a high power potential, and a second protection transistor connected between the terminal and a low power potential. The first and second protection transistors flow first and second off-leak currents. A current cancel circuit has a first monitor transistor for flowing a third off-leak current that is smaller than the first off-leak current, and a cancellation circuit for flowing the first off-leak current to the low power potential responsive to the third off-leak current. A current providing circuit has a second monitor transistor for flowing a fourth off-leak current that is smaller than the second off-leak current, and a providing circuit for providing the second off-leak current from the high power potential responsive to the fourth off-leak current.
대표청구항
▼
An off-leak current cancel circuit includes an input protection circuit having a first protection transistor connected between a terminal and a high power potential, and a second protection transistor connected between the terminal and a low power potential. The first and second protection transisto
An off-leak current cancel circuit includes an input protection circuit having a first protection transistor connected between a terminal and a high power potential, and a second protection transistor connected between the terminal and a low power potential. The first and second protection transistors flow first and second off-leak currents. A current cancel circuit has a first monitor transistor for flowing a third off-leak current that is smaller than the first off-leak current, and a cancellation circuit for flowing the first off-leak current to the low power potential responsive to the third off-leak current. A current providing circuit has a second monitor transistor for flowing a fourth off-leak current that is smaller than the second off-leak current, and a providing circuit for providing the second off-leak current from the high power potential responsive to the fourth off-leak current. rising determining which of said plurality of delayed signals is to comprise said selected m delayed signals, wherein: in a case that said currently-selected fine adjustment delay signal is switched to a fine adjustment delay signal whose phase leads by said time interval dtc'a phase of said currently-selected fine adjustment delay signal, a delayed signal from said plurality of delayed signals selected to become one of said m selected delay signals comprises a delayed signal whose phase leads a phase of said coarse adjustment delay signal to be switched by a time interval (m×dtc); and in a case that said currently-selected fine adjustment delay signal is switched to a fine adjustment delay signal whose phase lags a phase of said currently-selected fine adjustment delay signal by said time interval dtc', a delayed signal from said plurality of delayed signals selected to become one of said m selected delay signals comprises a delayed signal whose phase lags a phase of said coarse adjustment delay signal to be switched by the time interval (m×dtc). 4. A two step variable length delay circuit, comprising: a coarse adjustment delay circuit having three or more delay elements connected in series, each said delay element having a delay time dtc, said coarse adjustment delay circuit outputting a corresponding number of delay element output signals, a first delay element in said coarse adjustment delay circuit receiving an input clock signal; a first selection switching circuit that selects m of said delay element output signals (m is an integer being 3 or more), said m selected delay element output signals being first to mth signals; a waveform mixing circuit which receives said first to mth signals as first to mth inputs and provides 2m output signals, said 2m output signals comprising: said m delay element output signals, as amplified; and m mixed output signals, comprising: m-1 mixed signals, each being a signal whose phase is midway between an nth (n is an integer being 1 or more and (m-1) or less) input and an (n+1)th input of said first to mth inputs, said (m-1) mixed output signals being generated by mixing waveforms of said nth input and said (n+1)th input; and one mixed output signal whose phase is midway between the first input and the mth input; and a second selection switching circuit that selects one of the 2m outputs from said waveform mixing circuit to be a selected delay output signal. 5. A two step variable length delay circuit in accordance with claim 4, wherein, for said 2m output signals: said waveform mixing circuit amplifies: said nth input to become a (2n-1)th output; and said mth input to become a (2m-1)th output; and said waveform mixing circuit mixes: said nth input and said (n+1)th input to become a 2nth output; and said mth input and said first input to become a 2mth output, such that a phase difference between a jth output (j is an integer being 1 or more and (2m-2) or less) and a (j+1)th output is (dtc/2), and when an output from said delay elements is selected so that an input having a phase leading said first input by said time interval dtc is selected to be inputted to said mth input, the phase difference between the (2m-1)th output and the 2mth output becomes the time interval (dtc/2)]. 6. A two step variable length delay circuit in accordance with claim 4, wherein said waveform mixing circuit comprises a ring interpolator RIa, said ring interpolator RIa, comprising: a plurality of m buffers that respectively amplify each of said first to mth inputs; a plurality of (m-1) interpolators IPx (x is an integer being 1 or more and (m-1) or less); and an mth interpolator IPm, wherein: at each of said (m-1) interpolators IPx, the nth input is inputted to a phase lead input and the (n+1)th input is inputted to a phase lag input, each of said (m-1) interpolators IPx amplifies the nth input and the (n+1)th input and connects both these amplified inputs to genera te an output whose phase is midway between the phases of the nth and the (n+1)th inputs by mixing waveforms of both the inputs, and said mth interpolator Ipm, in which the mth input is inputted to a phase lead input and the first input is inputted to a phase lag input, amplifies the mth input and the first input and connects both the amplified mth and first inputs to generate an output whose phase is midway between the phases of the mth and the first inputs by mixing waveforms of both the inputs. 7. A two step variable length delay circuit in accordance with claim 6, wherein: when two signals whose phases are different from each other are inputted to said ring interpolator, and in a case that a phase lead signal is inputted to a buffer B3 and a phase lag signal is inputted to a buffer B4, and said interpolator IPx and said interpolator IPm include a buffer B1 to which said phase lead signal is inputted and a buffer B2 to which said phase lag signal is inputted, resistance values of transistors of said buffers B1 and B2 are set so that the phase of the signal at the output node to which the outputs from said buffers B1 and B2 are connected becomes a phase midway between the phase of the output from said buffer B3 and the phase of the output from said buffer B4. 8. A two step variable length delay circuit in accordance with claim 7, wherein: each said buffer B1, B2, B3, and B4 comprises one of an amplifier and an inverter. 9. A two step variable length delay circuit in accordance with claim 4, wherein each said delay element comprises a digital circuit that has delay time of said time interval dtc. 10. A two step variable length delay circuit in accordance with claim 4, further comprising: first controller that sends a first selection signal to said first selection switching circuit to select said m delay element output signals; and second controller that sends a second selection signal to said second selection switching circuit to select said output signal from said outputs of said waveform circuit. 11. A two step variable length delay circuit in accordance with claim 10, wherein: when said first controller receives a first delaying signal that makes the output from said waveform mixing circuit currently selected by said second selection switching circuit switch to an output having more phase lead, said first controller causes to be unselected one of said m selected delay element output signals not currently being used to generate said selected delay output signal, and said first controller causes said first selection switching circuit to switch to an output from a delay element whose phase is leading by the time interval (m×dtc), and controls said first selection switching circuit to select m sequential outputs from said delay elements. 12. A two step variable length delay circuit in accordance with claim 11, wherein: said one of said m selected delay element output signals to be unseleced when said first delaying signal is received comprises the one meeting the following two criteria: first, a one for which there is a largest phase difference from that of a selected delay element output signal currently being used to generate the output currently selected at the time of switching by said second selection means, and second, a one for which there is a smaller phase difference between: an output from said waveform mixing circuit that a delay element output signal, after having been switched, is amplified and an output from said waveform mixing selected after said switching; and an output from said waveform mixing circuit that the delay element output signal to be switched is amplified and the output from said waveform mixing circuit that is currently selected at the time of switching. 13. A two step variable length delay circuit in accordance with claim 11, wherein: in a case that a pth output (p is an integer being 2 or more and 2m or less) from said waveform mixing circuit is curren
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