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In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first software-pipelined instruction schedule based on an intermediate representation that has data flow inf

In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first software-pipelined instruction schedule based on an intermediate representation that has data flow information in SSA form. The scheduler-assigner also includes a rotating register allocator that designates live ranges of loop-variant variables in the first software-pipelined instruction schedule as being allocated to rotating registers, when available. The first software-pipelined instruction schedule may be a modulo schedule. When a rotating register is not available, the software-pipelined instruction scheduler may generate a second software-pipelined instruction schedule having an initiation interval greater than the initiation interval of the first software-pipelined instruction schedule.

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In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first software-pipelined instruction schedule based on an intermediate representation that has data flow inf

In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first software-pipelined instruction schedule based on an intermediate representation that has data flow information in SSA form. The scheduler-assigner also includes a rotating register allocator that designates live ranges of loop-variant variables in the first software-pipelined instruction schedule as being allocated to rotating registers, when available. The first software-pipelined instruction schedule may be a modulo schedule. When a rotating register is not available, the software-pipelined instruction scheduler may generate a second software-pipelined instruction schedule having an initiation interval greater than the initiation interval of the first software-pipelined instruction schedule. ep (b) comprises identifying a second subset of memory operations as cache miss memory operations where all memory operations in said plurality of instructions not chosen for said first subset of memory operations are in said second set of memory operations. 8. In the compilation system of claim 1; wherein identifying a first subset and a second subset comprises: identifying a cache-miss subset of memory operations as cache miss memory operations where each member of said subset is chosen using programmer input; identifying a cache-hit subset of memory operations as cache hit memory operations where all memory operations in said plurality of instructions not chosen for said first subset of memory operations are in said second subset of memory operations; and, calling said cache-hit subset a first subset, and calling said cache-miss subset a second subset. 9. In the compilation system of claim 1; wherein identifying a first subset and a second subset comprises: identifying a cache-miss subset of memory operations as cache miss memory operations where each member of said subset is chosen using cache profiling; identifying a cache-hit subset of memory operations as cache hit memory operations where all memory operations in said plurality of instructions not chosen for said first subset of memory operations are in said second subset of memory operations; and calling said cache-hit subset a first subset, and calling said cache-miss subset a second subset. 10. In the compilation system of claim 1, before identifying a first subset, the meth