초록 ▼

A cleaning implement, such as a floor mop, is provided. The cleaning implement includes a handle and a cleaning head attached to the handle. The cleaning head has at least one attachment structure for receiving and retaining a sheet about the cleaning head. The attachment structure includes a base t

A cleaning implement, such as a floor mop, is provided. The cleaning implement includes a handle and a cleaning head attached to the handle. The cleaning head has at least one attachment structure for receiving and retaining a sheet about the cleaning head. The attachment structure includes a base triangle and a plurality of substantially pie-shaped sections whose apexes meet at a substantially common point adjacent the base triangle. Two sides of the base triangle and two sides of each of the pie-shaped sections are defined by slits passing through the flexible material forming the attachment structure such that the base triangle and each of the pie-shaped sections can be deflected to receive the sheet.

대표청구항 ▼

A cleaning implement, such as a floor mop, is provided. The cleaning implement includes a handle and a cleaning head attached to the handle. The cleaning head has at least one attachment structure for receiving and retaining a sheet about the cleaning head. The attachment structure includes a base t

A cleaning implement, such as a floor mop, is provided. The cleaning implement includes a handle and a cleaning head attached to the handle. The cleaning head has at least one attachment structure for receiving and retaining a sheet about the cleaning head. The attachment structure includes a base triangle and a plurality of substantially pie-shaped sections whose apexes meet at a substantially common point adjacent the base triangle. Two sides of the base triangle and two sides of each of the pie-shaped sections are defined by slits passing through the flexible material forming the attachment structure such that the base triangle and each of the pie-shaped sections can be deflected to receive the sheet. rresponds to a first level of said integrated circuit design; (b) performing topology selection between said first set of bins and a root for a first clock tree; (c) discarding at least a portion of said first clock tree outside of said first level; and (d) performing topology selection between a second set of bins and a root for a second clock tree, wherein: said second set of bins corresponds to a second level of said integrated circuit design, said step (d) is based at least in part on said first clock tree, and said clock tree includes a portion of said first clock tree from said first set of bins and a portion of said second clock tree from said second set of bins. 2. A method according to claim 1, wherein said method further includes the step of: (e) approximating routing within each bin in said first set of bins. 3. A method according to claim 2, wherein said step (e) is performed prior to performing said step (b). 4. A method according to claim 1, wherein said topology selection is a bottom-up topology selection from said first set of bins up to said root for said first clock tree. 5. A method according to claim 1, wherein said method includes the step of: (f) buffering at least one segment of said first clock tree. 6. A method according o claim 5, wherein said step (f) is performed after performing said step (b) and before performing said step (c). 7. A method according to claim 5, wherein said step (f) results in insertion of at least one buffer in said first clock tree, wherein said at least one buffer is included in said clock tree. 8. A method according to claim 5, wherein said method further includes the step of: (g) sizing at least one segment of said first clock tree, wherein said step (g) is performed after performing said step (b) and before performing said step (c). 9. A method according to claim 8, wherein said step (g) results in sizing of at least one segment in said first clock tree, wherein said at least one segment in said first clock tree is included in said clock tree. 10. A method according to claim 1, wherein said method includes the steps of: (h) buffering at least one segment of said second clock tree; (j) discarding portions of said second clock tree above said second set of bins; and (k) constructing clock tree segments for bins in each level of said integrated circuit design above said second level, wherein said step (k) is based at least in part on said second clock tree. 11. A method according to claim 10, wherein said clock tree includes a clock tree segment for each level in said integrated circuit design. 12. A method according to claim 10, wherein each bin in said second set of bins includes at least one bin from said first set of bins. 13. A method according to claim 1, wherein each bin in said first set of bins is a quadrisection. 14. A method according to claim 1, wherein each bin in said first set of bins is a minimum size quadrisection. 15. A method according to claim 14 wherein said minimum size quadrisection is a quadrisection in which balanced routing is unnecessary. 16. A method according to claim 1, wherein said step (b) is performed without meandering. 17. A method according to claim 1, wherein said step (b) results in balancing delays to said latches distributed among said first set of bins. 18. A method according to claim 1, wherein said step (c) discards at least a portion of said first clock tree from said second set of bins. 19. A method according to claim 1, wherein said at least a portion of said first clock tree outside of said first level is all of said first clock tree outside of said first level. 20. A method according to claim 1, wherein said at least a portion of said first clock tree outside of said first level is all of said first clock tree above said first level. 21. A method for clock tree generation in an integrated circuit design, said method comprising the steps of: (a) distributing latches among a first set of bins, wher