초록 ▼

A snowmobile (20) having an engine (34) with an air charging system (70). The air charging system (70) is connected to an intercooler assembly (57), which includes a heat exchanger (56) mounted adjacent to an intercooler opening (48) in the track tunnel (36). A snow retention area (54) is located ab

A snowmobile (20) having an engine (34) with an air charging system (70). The air charging system (70) is connected to an intercooler assembly (57), which includes a heat exchanger (56) mounted adjacent to an intercooler opening (48) in the track tunnel (36). A snow retention area (54) is located above the heat exchanger (56) allowing for snow/ice to be thrown from a snowmobile drive track (38) and build up on top of the heat exchanger (56), allowing the snow/ice to absorb heat from intercooler assembly (57).

대표청구항 ▼

A snowmobile (20) having an engine (34) with an air charging system (70). The air charging system (70) is connected to an intercooler assembly (57), which includes a heat exchanger (56) mounted adjacent to an intercooler opening (48) in the track tunnel (36). A snow retention area (54) is located ab

A snowmobile (20) having an engine (34) with an air charging system (70). The air charging system (70) is connected to an intercooler assembly (57), which includes a heat exchanger (56) mounted adjacent to an intercooler opening (48) in the track tunnel (36). A snow retention area (54) is located above the heat exchanger (56) allowing for snow/ice to be thrown from a snowmobile drive track (38) and build up on top of the heat exchanger (56), allowing the snow/ice to absorb heat from intercooler assembly (57). e storage space formed by the storage units is configured as logical units to store data. Storage units are added to the array to form an expanded storage space. The storage units in the array prior to the addition of the storage units are in a pre-expansion storage space. At least one additional logical unit is configured in the expanded storage space such that the logical units existing prior to the addition of the storage units in the pre-expansion storage space are not affected by the logical units configured in the expanded storage space. y of memories through a bus group; a central processing unit to be coupled to said plurality of memories via said bus interface circuit, said central processing unit operating using said memories; a download circuit to be connected to said plurality of memories via said bus interface circuit, and carrying out data input/output with respect to said plurality of memories; a first reset signal generation circuit generating and applying to said central processing unit a first reset signal to reset said central processing unit; a second reset signal generation circuit generating and applying to said plurality of memories and said bus interface circuit a second reset signal according to a mode set signal and said first reset signal; a selector selectively coupling said central processing unit and said download circuit to said bus interface circuit in response to a predetermined selector control signal; and a selector control signal generation circuit generating and applying to said selector said selector control signal according to said mode set signal, an access request signal output to said bus interface circuit from said central processing unit and an access request signal output from said download circuit output to said bus interface circuit, and preferentially in response to the access request signal from said central processing unit. 10. The microcomputer according to claim 9, wherein said central processing unit outputs a first access request signal taking a first value representing true by a predetermined logic when access is requested to one of said memories, and taking a second value representing false by said logic when access is not requested, wherein said download circuit outputs a second access request signal taking said first value when access to said memories is requested, and taking said second value when access is not requested, said mode set signal taking said first value when input/output by said download circuit is specified, and otherwise said second value, wherein said selector control signal generation circuit includes a first logic circuit providing said selector control signal in response to said first access request signal, said second access request signal and said mode set signal. 11. The microcomputer according to claim 10, wherein said first logic circuit comprises first AND gate having a first input receiving an inversion of said first access request signal, a second input receiving said second access request signal, and an output, and an OR gate having a first input coupled to an output of said first AND gate, a second input coupled to said mode set signal, and an output coupled to said selector control signal. 12. The microcomputer according to claim 11, wherein said selector selects and couples said download circuit to one of said memories in response to said first value of said selector control signal, and selects and couples said central processing unit to one of said memories in response to said second value of said selector control signal. 13. The microcomputer according to claim 9, wherein said second reset signal generation circuit includes a logic circuit having a first input receiving said first reset signal, a second input receiving said mode set signal, and an output coupled to said second reset signal. 14. The microcomputer according to claim 13, wherein said central processing unit stops its operation when said first reset signal attains said first value, and starts its operation when said first reset signal attains said second value. 15. The microcomputer according to claim 14, wherein said plurality of memories and said bus interface circuit are all reset and stop their operation when said second reset signal takes said first value, and attain an operable state when said second reset signal takes said second value. 16. The microcomputer according to claim 15, wherein said logic circuit includes a second AND gate having a first input receiving an inversion of said