IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0235411
(2002-09-05)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
5 인용 특허 :
49 |
초록
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Engine nacelles for use with aircraft. In one embodiment, an engine nacelle includes an inlet having an inlet aperture and an outlet having an outlet aperture. In one aspect of this embodiment, the engine nacelle further includes a first side portion, a second side portion, and a third side portion.
Engine nacelles for use with aircraft. In one embodiment, an engine nacelle includes an inlet having an inlet aperture and an outlet having an outlet aperture. In one aspect of this embodiment, the engine nacelle further includes a first side portion, a second side portion, and a third side portion. The first side portion can extend at least generally between a first edge portion of the inlet aperture and a third edge portion of the outlet aperture. The second side portion can be offset from the first side portion and extend at least generally between a second edge portion of the inlet aperture and a fourth edge portion of the outlet aperture to define a first interior portion. The third side portion can be offset from the second side portion and extend at least generally from the second edge portion of the inlet aperture toward the fourth edge portion of the outlet aperture to define a second interior portion. In another aspect of this embodiment, the first interior portion is configured to house an engine, and the second interior portion is configured to house a landing gear assembly.
대표청구항
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Engine nacelles for use with aircraft. In one embodiment, an engine nacelle includes an inlet having an inlet aperture and an outlet having an outlet aperture. In one aspect of this embodiment, the engine nacelle further includes a first side portion, a second side portion, and a third side portion.
Engine nacelles for use with aircraft. In one embodiment, an engine nacelle includes an inlet having an inlet aperture and an outlet having an outlet aperture. In one aspect of this embodiment, the engine nacelle further includes a first side portion, a second side portion, and a third side portion. The first side portion can extend at least generally between a first edge portion of the inlet aperture and a third edge portion of the outlet aperture. The second side portion can be offset from the first side portion and extend at least generally between a second edge portion of the inlet aperture and a fourth edge portion of the outlet aperture to define a first interior portion. The third side portion can be offset from the second side portion and extend at least generally from the second edge portion of the inlet aperture toward the fourth edge portion of the outlet aperture to define a second interior portion. In another aspect of this embodiment, the first interior portion is configured to house an engine, and the second interior portion is configured to house a landing gear assembly. aslee et al., 345/467; US-5471575, 19951100, Giansante, 715/503; US-5710900, 19980100, Anand et al., 345/764; US-5799325, 19980800, Rivette et al., 715/500; US-5802352, 19980900, Chow et al., 707/517; US-5809266, 19980900, Touma et al., 345/764; US-5818850, 19981000, Tsai et al., 714/741; US-5835916, 19981100, Inaki et al., 707/509; US-5852819, 19981200, Beller, 707/001; US-5870746, 19990200, Knutson et al., 707/101; US-5999193, 19991200, Conley et al., 345/440; US-6047298, 20000400, Morishita, 715/532; US-6195653, 20010200, Bleizeffer et al., 707/002; US-6195665, 20010200, Jarett, 707/500 m 1, wherein the pattern to be generated is one of a physical pattern, a logical pattern and a checker pattern. 10. A semiconductor memory chip comprising: a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing bitlines and wordlines, the data being provided on input/output pins; and a pattern generator formed on the memory chip, the pattern generator further comprising: a programmable memory array including a plurality of memory banks, the memory banks having memory cells arranged in rows and columns, each bank being capable of storing data for a pattern to be generated for each of the input/output pins of the first memory array; means for addressing the data stored in the programmable memory array to address individual pattern data to be transmitted to and from the first memory array on input/output pins; a pattern decoder for selecting a pattern from a plurality of patterns, stored in the memory banks, in accordance with an input signal; and outputs of the pattern generator coupled to the input/output pins of the first memory array to provide the individual pattern data to be transmitted to and from the first memory array on input/output pins. 11. The semiconductor memory chip as recited in claim 10, wherein the means for addressing is included on the semiconductor memory chip. 12. The semiconductor memory chip as recited in claim 10, wherein the means for addressing is provided by an external testing device. 13. The semiconductor memory chip as recited in claim 10, wherein the input signal is provided from an external source off the memory chip. 14. The semiconductor memory chip as recited in claim 10, wherein the programmable memory array includes read only memory having pattern data stored therein. 15. The semiconductor memory chip as recited in claim 10, wherein the memory chip is a dynamic random access memory chip. 16. The semiconductor memory chip as recited in claim 10, wherein each of the plurality of patterns is stored on a number of memory banks. 17. The semiconductor memory chip as recited in claim 10, wherein the pattern to be generated is one of a physical pattern, a logical pattern and a checker pattern. 18. A DRAM memory chip comprising: a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing bitlines and wordlines, the data provided on input/output pins; and a pattern generator formed on the memory chip, the pattern generator further comprising: a programmable memory array including a plurality of memory banks, the memory banks having memory cells arranged in rows and columns, each bank being capable of storing data for a pattern to be generated for each of the input/output pins of the first memory array; input means for inputting the pattern data from a source external to the memory chip to the memory banks of the programmable memory, the pattern data being provided prior to testing the memory chip; means for addressing the data stored in the programmable memory array to address individual data to be transmitted to and from the first memory array; a pattern decoder for selecting a pattern from a plurality of patterns, stored in the memory banks, in accordance with an input signal; and outputs coupled to the input/output pins of the first memory array to provide the individual data to be transmitted to and from the first memory array. 19. The semiconductor memory chip as recited in claim 18, wherein the programmable memory array includes read only memory having pattern data stored therein. 20. The semiconductor memory chip as recited in claim 18, wherein the means for addressing is included on the semiconductor memory chip. 21. The semiconductor memory chip as recited in claim 18, wherein the input signal is provided from an external source o ff the memory chip. lay associated therewith is equal to zero; (c) when the delay associated with said one of the block units of the incoming stream is not equal to zero, generating a reading index for reading one of the block units stored in the data buffer, controlling the multiplexer to output said one of the block units read from the data buffer, generating a writing index, and storing said one of the block units of the incoming stream in the data buffer in accordance with the writing index; and (d) repeating steps (b) and (c) for succeeding ones of the block units of the incoming stream. 9. The method of claim 8, wherein the reading index is generated by incrementing a variable (i) under modulo N conditions. 10. The method of claim 8, wherein the writing index is equal to a remainder of the quotient of the sum of the index of the block unit in the corresponding data block of the incoming stream and the delay associated therewith, divided by the number (N). 11. The method of claim 8, further comprising the steps of: configuring the data buffer to have a number of lines equal to (N-1), each of which is used to store a respective one of the 1stto (N-1)th block units, each of the lines having a size sufficient to accommodate a predetermined number of the block units, the predetermined number being a smallest integer equal to or larger than a quotient of the delay associated with the respective one of the 1stto (N-1)th block units divided by the number (N); the lines of the data buffer being read sequentially when outputting the block units stored in the data buffer; for the lines of the data buffer having a size sufficient to accommodate more than one of the block units, the block units being stored and read therefrom in a first-in, first-out manner. 12. The method of claim 11, further comprising the steps of, after writing operation of the lines of the data buffer, checking address boundary conditions of the lines, and resetting a subsequent memory access address for the lines to a predetermined starting address when the subsequent memory access address does not fall within the address boundary conditions. 13. An apparatus for interleaving an incoming stream of data blocks, the interleaving being accomplished at a predetermined interleaving depth (D), each of the data blocks having a predetermined number (N) of block units indexed consecutively from 0 to (N-1), wherein a first one of the block units has no delay associated therewith, and subsequent ones of the block units in a designated one of the data blocks have a delay equal to (D-1) more than an immediately preceding one of the block units in the designated one of the data blocks, said apparatus comprising: a data buffer configured to have a number of lines equal to (N-1), each of which is used to store a respective one of the 1stto (N-1)th block units, each of the lines having a size sufficient to accommodate a predetermined number of the block units, the predetermined number being a smallest integer equal to or larger than a quotient of the delay associated with the respective one of the 1stto (N-1)th block units divided by the number (N); output means for outputting one of the block units of the incoming stream directly when the delay associated therewith is equal to zero; and control means for, when the delay associated with said one of the block units of the incoming stream is not equal to zero, generating a reading index-for reading one of the block units stored in said data buffer, controlling said output means to output said one of the block units read-from said data buffer, generating a writing index, and storing said one of the block units of the incoming stream in the respective one of the lines of said data buffer in accordance with the writing index. 14. The apparatus of claim 13, wherein said control means reads the lines of said data buffer sequentially when outputting the block units stored in said data buf fer. 15. The apparatus of claim 13, wherein the reading index is generated by incrementing a variable (i) under modulo N conditions. 16. The apparatus of claim 13, wherein the writing index is equal to a remainder of the quotient of the sum of the index of the block unit in the corresponding data block of the incoming stream and the delay associated therewith, divided by the number (N). 17. The apparatus of claim 13, wherein, for the lines of said data buffer having a size sufficient to accommodate more than one of the block units, said control means stores and reads the block units therefrom in a first-in, first-out manner. 18. The apparatus of claim 13, wherein, after writing operation of the lines of said data buffer, said control means checks address boundary conditions of the lines, and resets a subsequent memory access address for the lines to a predetermined starting address when the subsequent memory access address does not fall within the address boundary conditions. 19. The apparatus of claim 13, wherein said output means includes a multiplexer. 20. An apparatus for interleaving an incoming stream of data blocks, the interleaving being accomplished at a predetermined interleaving depth (D), each of the data blocks having a predetermined number (N) of block units indexed consecutively from 0 to (N-1), wherein a first one of the block units has no delay associated therewith, and subsequent ones of the block units in a designated one of the data blocks have a delay equal to (D-1) more than an immediately preceding one of the block units in the designated one of the data blocks, said apparatus comprising: a data buffer; a multiplexer connected to said data buffer and adapted to receive the incoming stream; and control means, connected to said data buffer and said multiplexer, for controlling said multiplexer to IS output one of the block units of the incoming stream when the delay associated therewith is equal to zero, and for, when the delay associated with said one of the block units of the incoming stream is not equal to zero, generating a reading index for reading one of the block units stored in said data buffer, controlling said multiplexer to output said one of the block units read from said data buffer, generating a writing index, and storing said one of the block units of the incoming stream in the data buffer in accordance with the writing index. 21. The apparatus of claim 20, wherein the reading index is generated by incrementing a variable (i) under modulo N conditions. 22. The apparatus of claim 20, wherein the writing index is equal to a remainder of the quotient of the sum of the index of the block unit in the corresponding data block of the incoming stream and the delay associated therewith, divided by the number (N). 23. The apparatus of claim 20, wherein: said data buffer is configured to have a number of lines equal to (N-1), each of which is used to store a respective one of the 1stto (N-1)th block units, each of the lines having a size sufficient to accommodate a predetermined number of the block units, the predetermined number being a smallest integer equal to or larger than a quotient of the delay associated with the respective one of the 1stto (N-1)th block units divided by the number (N); said control means reading the lines of said data buffer when outputting the block units stored in said data buffer; for the lines of the data buffer having a size sufficient to accommodate more than one of the block units, said control means storing and reading the block units therefrom in a first-in, first-out manner. 24. The apparatus of claim 23, wherein, after writing operation of the lines of said data buffer, said control means checks address boundary conditions of the lines, and resets a subsequent memory access address for the lines to a predetermined starting address when the subsequent memory access address does not fall within the address boundary conditions.
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