초록 ▼

Disclosed herein is a chip on board lead package for optical mice and lens cover for the same. A semiconductor chip on board package for optical mice has a board, a semiconductor chip, at least one circuit pattern, at least one bonding wire, and a lens cover. The board has top and bottom surfaces, a

Disclosed herein is a chip on board lead package for optical mice and lens cover for the same. A semiconductor chip on board package for optical mice has a board, a semiconductor chip, at least one circuit pattern, at least one bonding wire, and a lens cover. The board has top and bottom surfaces, and a pair of via holes. The semiconductor chip is attached to a center portion on the top surface of the board and provided with a plurality of electrode terminals. The circuit pattern is formed on the top surface of the board. The bonding wire electrically connects the electrode terminals of the semiconductor chip with the circuit pattern. The lens cover encloses the top surface of the board and has a lens disposed on the same axis as that of the semiconductor chip, a plurality of electrode pins formed at positions of the lens cover corresponding to the positions of the via holes in the board to be integrated with the lens cover, and an opening formed in a center portion within the lens cover.

대표청구항 ▼

Disclosed herein is a chip on board lead package for optical mice and lens cover for the same. A semiconductor chip on board package for optical mice has a board, a semiconductor chip, at least one circuit pattern, at least one bonding wire, and a lens cover. The board has top and bottom surfaces, a

Disclosed herein is a chip on board lead package for optical mice and lens cover for the same. A semiconductor chip on board package for optical mice has a board, a semiconductor chip, at least one circuit pattern, at least one bonding wire, and a lens cover. The board has top and bottom surfaces, and a pair of via holes. The semiconductor chip is attached to a center portion on the top surface of the board and provided with a plurality of electrode terminals. The circuit pattern is formed on the top surface of the board. The bonding wire electrically connects the electrode terminals of the semiconductor chip with the circuit pattern. The lens cover encloses the top surface of the board and has a lens disposed on the same axis as that of the semiconductor chip, a plurality of electrode pins formed at positions of the lens cover corresponding to the positions of the via holes in the board to be integrated with the lens cover, and an opening formed in a center portion within the lens cover. formed on the layer of insulation material over the first channel region. 3. The circuit of claim 2 and further comprising a third semiconductor material, the first semiconductor material and the second semiconductor material being wells formed in the third semiconductor material. 4. The circuit of claim 3 wherein the third semiconductor material is a substrate. 5. The circuit of claim 3 wherein the third semiconductor material is an epitaxial layer. 6. The circuit of claim 2 and further comprising: a second transistor having: a third semiconductor material of the second conductivity type, the third semiconductor material having a second channel region defined therein, the layer of insulation material being formed on the third semiconductor material; third source and drain regions of the first conductivity type formed in the third semiconductor material, the third source and drain regions being on opposite sides of the second channel region; fourth source and drain regions of the first conductivity type formed in the third semiconductor material, the fourth source and drain regions being on opposite sides of the second channel region and adjoining the third source and drain regions, respectively, the fourth source and drain regions having dopant concentrations that are greater than dopant concentrations of the third source and drain regions, and substantially equal to a dopant concentration of the second region; and a second MOS gate formed on the layer of insulation material over the second channel region. 7. The circuit of claim 6 and further comprising a fourth semiconductor material, the first semiconductor material, the second semiconductor material, and the third semiconductor material being wells formed in the fourth semiconductor material. 8. The circuit of claim 7 wherein the fourth semiconductor material is a substrate. 9. The circuit of claim 7 wherein the fourth semiconductor material is an epitaxial layer. 10. The circuit of claim 6 wherein the third semiconductor material is a substrate, and the first and second semiconductor materials are wells formed in the substrate. 11. The circuit of claim 6 wherein the third semiconductor material is an epitaxial layer, and the first and second semiconductor materials are wells formed in the epitaxial layer. 12. A varactor comprising: a semiconductor material having a surface and a first conductivity type; a layer of insulation material formed on the surface of the semiconductor material; a conductive region having a bottom surface formed on the layer of insulation material, and a side wall surface; a first region of a second conductivity type formed in the semiconductor material, the first region contacting the surface; a second region of the first conductivity type formed in the semiconductor material, the second region contacting the surface and the first region, the second region having a dopant concentration; and a region of the semiconductor material that includes a point, the point contacting both the first region and the surface vertically under the conductive region, the region of semiconductor material having the first conductivity type and a dopant concentration that is less than the dopant concentration of the second region. 13. The varactor of claim 12 wherein the region of the semiconductor material extends from the point to a first location that lies vertically under a center region of the conductive region. 14. The varactor of claim 13 wherein the region of the semiconductor material extends from the point to a second location, the first location lying between the second location and the point. 15. The varactor of claim 12 and further comprising a side wall spacer that contacts the conductive region. 16. The varactor of claim 15 wherein the side wall spacer contacts the side wall surface of the conductive region, substantially all of the first region lying vertically under the side wall spacer. 17. The varactor of claim 15 wherein th