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Method of manufacturing semiconductor wafer method of using and utilizing the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C30B-025/18
출원번호 US-0453539 (1999-12-03)
우선권정보 JP-0346116 (1998-12-04); JP-0084649 (1999-03-26); JP-0334544 (1999-11-25)
발명자 / 주소
  • Yonehara, Takao
  • Watanabe, Kunio
  • Shimada, Tetsuya
  • Ohmi, Kazuaki
  • Sakaguchi, Kiyofumi
출원인 / 주소
  • Canon Kabushiki Kaisha
대리인 / 주소
    Fitzpatrick, Cella, Harper & Scinto
인용정보 피인용 횟수 : 55  인용 특허 : 13

초록

A process for manufacturing a semiconductor wafer which has superior suitability for mass production and reproducibility. The process comprises the steps of preparing a first member which has a monocrystalline semiconductor layer on a semiconductor substrate with a separation layer arranged therebet

대표청구항

A process for manufacturing a semiconductor wafer which has superior suitability for mass production and reproducibility. The process comprises the steps of preparing a first member which has a monocrystalline semiconductor layer on a semiconductor substrate with a separation layer arranged therebet

이 특허에 인용된 특허 (13)

  1. Solomon Glenn S., Elimination of thermal mismatch defects in epitaxially deposited films through the separation of the substrate from the.
  2. Maracas George N. (Tempe AZ) Ruechner Ronald A. (Mesa AZ) Gerber Donald S. (Scottsdale AZ), Means and methods of lifting and relocating an epitaxial device layer.
  3. Lee Sahng Kyoo,KRX ; Park Sang Kyun,KRX, Method for fabricating semiconductor wafers.
  4. Milnes Arthur G. (Pittsburgh PA), Method for making thin film cadmium telluride and related semiconductors for solar cells.
  5. Matsushita Takeshi,JPX ; Tayanaka Hiroshi,JPX, Method for separating a device-forming layer from a base body.
  6. Takenaka Takao (Annaka JPX) Endo Masahisa (Gunma JPX) Yamada Masato (Annaka JPX), Method of making epitaxial wafers.
  7. Bozler Carl O. (Sudbury MA) Fan John C. C. (Chestnut Hill MA) McClelland Robert W. (Weymouth MA), Method of producing sheets of crystalline material.
  8. Sullivan Gerard J. (Thousand Oaks CA) Szwed Mary K. (Huntington Beach CA) Chang Mau-Chung F. (Thousand Oaks CA), Method of transferring a thin film to an alternate substrate.
  9. Sakaguchi Kiyofumi,JPX ; Yonehara Takao,JPX, Process for production of semiconductor substrate.
  10. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  11. Kenney Donald M., SOI fabrication method.
  12. Lawrence John E. (Cupertino CA), Semiconductor EPI on recycled silicon wafers.
  13. Yonehara Takao (Atsugi JPX), Semiconductor member and process for preparing semiconductor member.

이 특허를 인용한 특허 (55)

  1. Currie,Matthew T., Control of strain in device layers by prevention of relaxation.
  2. Currie,Matthew T., Control of strain in device layers by selective relaxation.
  3. Smart,Joseph; Hosse,Brook; Gibb,Shawn; Grider,David; Shealy,Jeffrey B., Epitaxy/substrate release layer.
  4. Wu,Kenneth C.; Fitzgerald,Eugene A.; Taraschi,Gianni; Borenstein,Jeffrey T., Etch stop layer system.
  5. Johnson, Joseph Herbert, Field effect transistor (FET) having fingers with rippled edges.
  6. Ebata,Makoto; Fujita,Fusao; Saito,Makoto, Film thickness measuring monitor wafer.
  7. Ritenour, Andrew P., Gallium nitride (GaN) device with leakage current-based over-voltage protection.
  8. Kobayashi, Kevin Wesley; Henry, Haldane S.; Ritenour, Andrew P., High voltage field effect transistor finger terminations.
  9. Kobayashi, Kevin Wesley; Henry, Haldane S.; Ritenour, Andrew P., High voltage field effect transitor finger terminations.
  10. Currie, Matthew T., Hybrid fin field-effect transistor structures and related methods.
  11. Moroz, Victor; Bomholt, Lars, Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same.
  12. Moroz, Victor; Bomholt, Lars, Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same.
  13. Sheridan, David Charles; Dry, Robert Charles; Willis, Don, Integrated power module with improved isolation and thermal conductivity.
  14. Ritenour, Andrew P., Lateral semiconductor device with vertical breakdown region.
  15. Akiyama,Yoshikazu, Manufacturing method of the active matrix substrate, and an electro-optical apparatus having the active matrix substrate.
  16. Nakata, Mitsuru; Takechi, Kazushige; Kanoh, Hiroshi, Manufacturing method of thin film device substrate.
  17. Noda, Kosei; Takeuchi, Toshihiko; Ishikawa, Makoto, Method for manufacturing SOI substrate and semiconductor device.
  18. Ohnuma, Hideto; Hirose, Takashi, Method for manufacturing photoelectric conversion device.
  19. Ritenour, Andrew P., Method for on-wafer high voltage testing of semiconductor devices.
  20. Orlowski,Marius K., Method for removing a semiconductor layer.
  21. Cheng,Zhiyuan; Fitzgerald,Eugene A.; Antoniadis,Dimitri A., Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers.
  22. Hanaoka, Kazuya; Tsuya, Hideki; Nagai, Masaharu, Method of manufacturing SOI substrate.
  23. Hanaoka, Kazuya; Tsuya, Hideki; Nagai, Masaharu, Method of manufacturing SOI substrate.
  24. Isaka, Fumito; Kato, Sho; Dairiki, Koji, Method of manufacturing photoelectric conversion device.
  25. Isaka, Fumito; Kato, Sho; Dairiki, Koji, Method of manufacturing photoelectric conversion device.
  26. Isaka, Fumito; Kato, Sho; Dairiki, Koji, Method of manufacturing photoelectric conversion device.
  27. Isaka, Fumito; Kato, Sho; Nei, Kosei; Komatsu, Ryu; Shimomura, Akihisa; Dairiki, Koji, Method of manufacturing photoelectric conversion device.
  28. Kobayashi, Kevin Wesley; Henry, Haldane S.; Ritenour, Andrew P., Methods for fabricating high voltage field effect transistor finger terminations.
  29. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.
  30. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming III-V semiconductor device structures.
  31. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain.
  32. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes.
  33. Moroz, Victor; Bomholt, Lars, Methods for manufacturing integrated circuit devices having features with reduced edge curvature.
  34. Moroz, Victor; Bomholt, Lars, Methods for manufacturing integrated circuit devices having features with reduced edge curvature.
  35. Currie,Matthew T., Methods of forming hybrid fin field-effect transistor structures.
  36. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods of forming strained-semiconductor-on-insulator device structures.
  37. Lochtefeld,Anthony J.; Langdo,Thomas A.; Hammond,Richard; Currie,Matthew T.; Braithwaite,Glyn; Fitzgerald,Eugene A., Methods of forming strained-semiconductor-on-insulator finFET device structures.
  38. Weng,Xiaojun; Goldman,Rachel S., Narrow energy band gap gallium arsenide nitride semi-conductors and an ion-cut-synthesis method for producing the same.
  39. Levesque, Chris; Kobayashi, Kevin Wesley; Nadimpalli, Praveen Varma; Clark, Ricke W., Power amplifier controller.
  40. Ritenour, Andrew P.; Partyka, Paul, Power device packaging having backmetals couple the plurality of bond pads to the die backside.
  41. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.
  42. Ritenour, Andrew P., Schottky gated transistor with interfacial layer.
  43. Ritenour, Andrew P., Semiconductor device having improved heat dissipation.
  44. Ritenour, Andrew P., Semiconductor device having improved heat dissipation.
  45. Cheng, Zhiyuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A., Semiconductor device structure.
  46. Ritenour, Andrew P., Semiconductor device with electrical overstress (EOS) protection.
  47. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained germanium-on-insulator device structures.
  48. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  49. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  50. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures with elevated source/drain regions.
  51. Langdo,Thomas A.; Currie,Matthew T.; Braithwaite,Glyn; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator finFET device structures.
  52. Albrecht, Peter D., Systems and methods for connecting an ingot to a wire saw.
  53. Kobayashi, Kevin Wesley, Transition frequency multiplier semiconductor device.
  54. Frantz, Jesse A.; Myers, Jason D.; Bekele, Robel Y.; Sanghera, Jasbinder S., Wet-etchable, sacrificial liftoff layer compatible with high temperature processing.
  55. Vetury, Ramakrishna; Shealy, Jeffrey Blanton, Wide bandwidth radio frequency amplier having dual gate transistors.
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