초록 ▼

A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator s

A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a. correlated result.

대표청구항 ▼

A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator s

A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a. correlated result. rcuit; a controllable first switching device, said first word line being connectable to said supply circuit via said controllable first switching device for one of reading from and writing to one of said memory cells; a controllable second switching device, said second word line being connectable to said supply circuit via said controllable second switching device for one of reading from and writing to one of said memory cells; and a control circuit connected to said first word line, said second word line, said controllable first switching device, and said controllable second switching device, said control circuit driving said controllable first switching device in dependence on a control activation state of a second word line input to said control circuit and driving said controllable second switching device in dependence on a control activation state of a first word line input to said control circuit. 2. The integrated memory according to claim 1, wherein: said memory cell array has at least two word line segments, said at least two word line segments include a first word line segment and a second word line segment; said first word line segment includes said first word line and said second word line; said second word line segment includes a third word line and a fourth word line; driver circuits respectively connecting said first word line and said third word line to one another and connecting said second word line and said fourth word line to one another; a controllable third switching device, said third word line being connectable to said supply circuit via said controllable third switching device; a controllable fourth switching device, said fourth word line being connectable to said supply circuit via said controllable fourth switching device; and a further control circuit, said first word line segment being assigned to said control circuit, said second word line segment being assigned to said further control circuit, said control circuit and said further control circuit being connected to associated ones of said first, second, third, and fourth word lines of a respective one of said first and second word line segments and to associated ones of said controllable first, second, third, and fourth switching devices. 3. The integrated memory according to claim 2, including: address terminals for providing an address signal; and said driver circuits being connectable to a respective one of said address terminals in order to activate a respective one of said driver circuits. 4. The integrated memory according to claim 1, including: an address terminal for providing an address signal; and said control circuit being connectable to said address terminal in order to activate said control circuit. 5. The integrated memory according to claim 1, including: a first address terminal for providing a first address signal; a second address terminal for providing a second address signal; said controllable first switching device and said controllable second switching device each having a control terminal; said control circuit including a first logic combination circuit and a second logic combination circuit; said first logic combination circuit having inputs respectively connected to said first address terminal for providing the first address signal and to said first word line; said first logic combination circuit having an output connected to said control terminal of said controllable second switching device; said second logic combination circuit having inputs respectively connected to said second address terminal for providing the second address signal and to said second word line; and said second logic combination circuit having an output connected to said control terminal of said controllable first switching device. 6. The integrated memory according to claim 5, wherein said first address terminal for providing the first address signal and said second address terminal for providing the second addr ess signal are connected to one another. 7. The integrated memory according to claim 1, wherein said supply circuit includes a current source connectable to said first word line and to said second word line. 8. The integrated memory according to claim 1, including: a semiconductor chip region including a plurality of memory cell arrays, said memory cell arrays defining respective planes, a first one of the planes extending above a second one of the planes; and said memory cells being disposed in said plurality of memory cell arrays such that said first word line is disposed in the first one of the planes and said second word line is disposed in the second one of the planes. 9. The integrated memory according to claim 1, wherein said memory cells have a magnetoresistive memory effect, and said memory cells are in each case connected between one of said bit lines and one of said word lines.