$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semiconductor package with molded flash 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0847470 (2001-05-02)
발명자 / 주소
  • Bolken, Todd O.
  • Peters, David L.
  • Tandy, Patrick W.
  • Cobbley, Chad A.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Gratton, Stephen A.
인용정보 피인용 횟수 : 22  인용 특허 : 14

초록

A method for fabricating a semiconductor package is performed using a mold tooling fixture having a mold cavity and a pair of flash control cavities on either side of the mold cavity. The semiconductor package includes a substrate and a semiconductor die attached to the substrate. The substrate incl

대표청구항

1. A semiconductor package comprising: a substrate; a molded encapsulant on the substrate comprising a plastic material having a peripheral edge; and a molded flash on the substrate comprising the plastic material contained in a flash area on the substrate having a selected width and at least p

이 특허에 인용된 특허 (14)

  1. Johnson Mark S. ; Bolken Todd O., Asymmetric transfer molding method and an asymmetric encapsulation made therefrom.
  2. Patrick W. Tandy ; Joseph M. Brand ; Brad D. Rumsey ; Steven R. Stephenson ; David J. Corisis ; Todd O. Bolken ; Edward A. Schrock ; Brenton L. Dickey, Controlling packaging encapsulant leakage.
  3. Tandy Patrick W. ; Brand Joseph M. ; Rumsey Brad D. ; Stephenson Steven R. ; Corisis David J. ; Bolken Todd O. ; Schrock Edward A. ; Dickey Brenton L., Controlling packaging encapsulant leakage.
  4. Jones Tim (Chandler AZ) Ommen Denise (Phoenix AZ) Baird John (Scottsdale AZ), Low-profile ball-grid array semiconductor package and method.
  5. Chang Daniel,TWX ; Huang Chengder,TWX ; Tsao Pei-Haw,TWX, Magnetic insert into mold cavity to prevent resin bleeding from bond area of pre-mold (open cavity) plastic chip carrier during molding process.
  6. Bolken Todd O. ; Peters David L. ; Tandy Patrick W. ; Cobbley Chad A., Method for fabricating semiconductor packages using mold tooling fixture with flash control cavities.
  7. Chung Myung Kee,KRX ; Lee Jin Soon,KRX ; Jin Ho Tae,KRX ; Hong In Pyo,KRX, Method for manufacturing semiconductor package of center pad type device.
  8. Steffen Francis (Rousset FRX), Method of encapsulating an integrated circuit using a punched metal grid attached to a perforated dielectric strip.
  9. Manzione Louis T. (Summit NJ) Weld John D. (Succasunna NJ), Method of encapsulating large substrate devices using reservoir cavities for balanced mold filling.
  10. Akhavain Mohammad (San Diego CA) Economy Ken W. (Escondido CA), Method of fabricating integrated circuit module.
  11. Campbell Jeffrey S. ; Holton James T., Molded electrical connector with a deformable elastic ridge.
  12. Lee Kyu Jin,KRX ; Choi Wan Gyun,KRX, Semiconductor chip package using flexible circuit board with central opening.
  13. Lee Shaw Wei ; Lee Poh Ling,SGX ; Panczak Anthony E., Substrate board having an anti-adhesive solder mask.
  14. Massingill Thomas J. (Scotts Valley CA), Thin cavity down ball grid array package based on wirebond technology.

이 특허를 인용한 특허 (22)

  1. Bolken,Todd O.; Cobbley,Chad A., Ball grid array packages with thermally conductive containers.
  2. Moden, Walter, Chip scale image sensor package.
  3. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Circuit and substrate encapsulation methods.
  4. Bolken, Todd O., Flip chip integrated package mount support.
  5. Moden,Walter, Imaging system.
  6. Jang, Ki Youn; Song, Sungmin; Bae, JoHyun, Integrated circuit package system employing mold flash prevention technology.
  7. Jang, Ki Youn; Song, Sungmin; Bae, JoHyun, Integrated circuit package system employing mold flash prevention technology.
  8. Kuan, Heap Hoe; Chua, Pei Ee; Chow, Seng Guan, Integrated circuit package system employing resilient member mold system technology.
  9. Moden, Walter, Method for fabricating image sensor semiconductor package.
  10. James,Steven L.; Tandy, deceased,William D.; Tandy, legal representative,Lori, Method for fabricating semiconductor components using mold cavities having runners configured to minimize venting.
  11. Kwang, Chua Swee; Poo, Chia Yong, Method for fabricating semiconductor packages with discrete components.
  12. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Packages for semiconductor die.
  13. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Packages for semiconductor die.
  14. James,Steven L.; Tandy, legal representative,Lori; Tandy, deceased,William D., Semiconductor component having dummy segments with trapped corner air.
  15. Hall, Frank L.; Baerlocher, Cary J., Semiconductor integrated circuit package having electrically disconnected solder balls for mounting.
  16. Hall,Frank L.; Baerlocher,Cary J., Semiconductor integrated circuit package having electrically disconnected solder balls for mounting.
  17. Hall,Frank L.; Baerlocher,Cary J., Semiconductor integrated circuit package having electrically disconnected solder balls for mounting.
  18. Hall,Frank L.; Baerlocher,Cary J., Semiconductor integrated circuit package having electrically disconnected solder balls for mounting.
  19. Hall,Frank L.; Baerlocher,Cary J., Semiconductor integrated circuit package having electrically disconnected solder balls for mounting.
  20. Kwang, Chua Swee; Poo, Chia Yong, Semiconductor package having die with recess and discrete component embedded within the recess.
  21. Kwang, Chua Swee; Poo, Chia Yong, Stacked semiconductor package having discrete components.
  22. James, Steven L.; Tandy, legal representative, Lori, System for fabricating semiconductor components using mold cavities having runners configured to minimize venting.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로