초록 ▼

A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI l

A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.

대표청구항 ▼

1. A method of forming a sub-0.05 μm channel length fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device comprising the steps of: forming at least one dummy gate region atop a silicon-on-insulator (SOI) layer, said dummy gate region comprisin

1. A method of forming a sub-0.05 μm channel length fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device comprising the steps of: forming at least one dummy gate region atop a silicon-on-insulator (SOI) layer, said dummy gate region comprising at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of said sacrificial polysilicon region; forming an oxide layer that is coplanar with an upper surface of said dummy gate region; removing said sacrificial polysilicon region to expose a portion of the SOI layer; forming a thinned device channel region by utilizing at least an etching step in said exposed portion of the SOI layer, said etching step comprising chemical down stream etching, reactive ion etching or thermal oxidation and reactive-ion etching; forming inner nitride spacers on exposed walls of said first nitride spacers; forming a gate region over said thinned device channel region; and removing said oxide layer so as to expose thicker portions of said SOI layer than said device channel region. 2. The method of claim 1 wherein said sacrificial polysilicon region is removed using chemical downstream etching or a KOH etchant. 3. The method of claim 1 wherein said forming of said thinned device channel region further comprises implantation and annealing which are performed prior to the etching step. 4. The method of claim 1 wherein said inner nitride spacers are formed by deposition and etching. 5. The method of claim 1 wherein said thinned device region is subjected to a thermal oxidation and chemical oxide removal (COR) process prior to forming said gate region. 6. The method of claim 5 wherein said COR process is carried out at a pressure of about 6 millitorr or less in a vapor of HF and NH3. 7. The method of claim 1 further comprising a step of forming at least source/drain regions into said SOI layer in regions adjacent to said thinned device channel region. 8. The method of claim 7 wherein said source/drain regions are formed during formation of the dummy gate region. 9. The method of claim 7 wherein said source/drain regions are formed after said oxide layer has been removed. 10. The method of claim 1 further comprising forming salicide regions on said thicker portions of said SOI layer.