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A system for producing a raster image derived from coded and non-coded portions of a hybrid data structure from an input bitmap including (1) a data processing apparatus, (2) a recognizer which performs recognition on an input bitmap to the data processing apparatus to detect identifiable objects wi

A system for producing a raster image derived from coded and non-coded portions of a hybrid data structure from an input bitmap including (1) a data processing apparatus, (2) a recognizer which performs recognition on an input bitmap to the data processing apparatus to detect identifiable objects within the input bitmap, (3) a mechanism for producing a hybrid data structure including coded data corresponding to the identifiable objects and non-coded data derived from portions of the input bitmap which do not correspond to the identifiable objects, and (4) an output device capable of developing a visually perceptible raster image derived from the hybrid data structure. The raster image includes raster images of the identifiable objects and raster images derived from portions of the input bitmap that do not correspond to the identifiable objects. The invention includes a method for producing a hybrid data structure for a bitmap of an image having the steps of: (1) inputting a signal comprising a bitmap into a digital processing apparatus, (2) partitioning the bitmap into a hierarchy of lexical units, (3) assigning labels to a label list for each lexical unit of a predetermined hierarchical level, where labels in the label list have an associated confidence level, and (4) storing each lexical unit in a hybrid data structure as either an identifiable object or a non-identifiable object.

대표청구항 ▼

A system for producing a raster image derived from coded and non-coded portions of a hybrid data structure from an input bitmap including (1) a data processing apparatus, (2) a recognizer which performs recognition on an input bitmap to the data processing apparatus to detect identifiable objects wi

A system for producing a raster image derived from coded and non-coded portions of a hybrid data structure from an input bitmap including (1) a data processing apparatus, (2) a recognizer which performs recognition on an input bitmap to the data processing apparatus to detect identifiable objects within the input bitmap, (3) a mechanism for producing a hybrid data structure including coded data corresponding to the identifiable objects and non-coded data derived from portions of the input bitmap which do not correspond to the identifiable objects, and (4) an output device capable of developing a visually perceptible raster image derived from the hybrid data structure. The raster image includes raster images of the identifiable objects and raster images derived from portions of the input bitmap that do not correspond to the identifiable objects. The invention includes a method for producing a hybrid data structure for a bitmap of an image having the steps of: (1) inputting a signal comprising a bitmap into a digital processing apparatus, (2) partitioning the bitmap into a hierarchy of lexical units, (3) assigning labels to a label list for each lexical unit of a predetermined hierarchical level, where labels in the label list have an associated confidence level, and (4) storing each lexical unit in a hybrid data structure as either an identifiable object or a non-identifiable object. y determine an occurrence of a stockout of the object by simple data processing without performing pattern recognition on a radiation perspective image. with a change from said second logic to said first logic of said clock signal; and a second latch circuit having a mode of capturing an output of said first latch circuit received by a second node synchronously with a change from said second logic to said first logic of said clock signal and a mode of holding an output of said first latch circuit captured from said second node synchronously with a change from said first logic to said second logic of said clock signal. 3. A counter circuit for counting a clock signal, comprising a plurality of cascade-connected counter stages for commonly receiving said clock signal, each of said plurality of counter stages including a flip-flop circuit for capturing an input signal in response to said clock signal and outputting an output signal corresponding to said input signal, at least one of said plurality of counter stages being a first arithmetic counter stage, and said first arithmetic counter stage further including a first two-input logic gate for receiving, as a first internal input signal, an output of said flip-flop circuit included in said first arithmetic counter stage, receiving, as a second internal input signal, an output of said flip-flop circuit included in a predetermined counter stage different from said first arithmetic counter stage in said plurality of counter stages, and outputting a result of logical operation of said first and second internal input signals to a counter stage at a subsequent stage of said first arithmetic counter stage, wherein when N is an integer not smaller than two, said plurality of counter stages are first to N-th cascade-connected counter stages in which a counter stage at the first stage is the first counter stage and a counter stage at the final stage is the N-th counter stage, said predetermined counter stage is said N-th counter stage, and when m is an integer satisfying the relation of N/2≤m+1, first to m-th counter stages out of said first to N-th counter stages are said first arithmetic counter stages, wherein m is equal to N-1. 4. The counter circuit according to claim 3, wherein said flip flop circuit includes a first latch circuit having a mode of capturing said input signal received by a first node synchronously with a change from a first logic to a second logic of said clock signal and a mode of holding said input signal captured from said first node synchronously with a change from said second logic to said first logic of said clock signal; and a second latch circuit having a mode of capturing an output of said first latch circuit received by a second node synchronously with a change from said second logic to said first logic of said clock signal and a mode of holding an output of said first latch circuit captured from said second node synchronously with a change from said first logic to said second logic of said clock signal. 5. A counter circuit for counting a clock signal, comprising a plurality of cascade-connected counter stages for commonly receiving said clock signal, each of said plurality of counter stages including a flip-flop circuit for capturing an input signal in response to said clock signal and outputting an output signal corresponding to said input signal, at least one of said plurality of counter stages being a first arithmetic counter stage, and said first arithmetic counter stage further including a first two-input logic gate for receiving, as a first internal input signal, an output of said flip-flop circuit included in said first arithmetic counter stage, receiving, as a second internal input signal, an output of said flip-flop circuit included in a predetermined counter stage different from said first arithmetic counter stage in said plurality of counter stages, and outputting a result of logical operation of said first and second internal input signals to a counter stage at a subsequent stage of said first arithmetic counter stage, wherein said flip-flop circuit outputs a po