초록 ▼

A method and system for monitoring performance of a program is provided. A trace record containing a call stack associated with the program is periodically generated. An occurrence of a selected event or a timer interrupt is detected, and in response, an execution context sample is obtained that con

A method and system for monitoring performance of a program is provided. A trace record containing a call stack associated with the program is periodically generated. An occurrence of a selected event or a timer interrupt is detected, and in response, an execution context sample is obtained that contains a process identifier, a thread identifier, a program counter, and a stack pointer. A trace record containing the execution context sample data is generated. During post-processing, the execution context samples are compared with a call stack to identify the routine associated with the execution sample data.

대표청구항 ▼

A method and system for monitoring performance of a program is provided. A trace record containing a call stack associated with the program is periodically generated. An occurrence of a selected event or a timer interrupt is detected, and in response, an execution context sample is obtained that con

A method and system for monitoring performance of a program is provided. A trace record containing a call stack associated with the program is periodically generated. An occurrence of a selected event or a timer interrupt is detected, and in response, an execution context sample is obtained that contains a process identifier, a thread identifier, a program counter, and a stack pointer. A trace record containing the execution context sample data is generated. During post-processing, the execution context samples are compared with a call stack to identify the routine associated with the execution sample data. ld macro; generating a complete physical implementation of the parent macro; and passing third physical constraints information of final detailed routing and repeaters placed in the common area from the parent macro to the child macro. 3. The method of claim 2 further comprising generating a complete physical implementation of the child macro at the child level in response to the third physical constraints information of locations of the repeaters and the final detailed routing passed from the parent macro. 4. A method of hierarchical repeater insertion comprising: defining an initial floorplan of a parent macro in a hierarchical circuit design; passing outline and pin locations from the initial floorplan from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan of the child macro in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing first physical constraints information from the child macro to the parent macro; determining an ideal location for a repeater in the common area in response to the first physical constraints information; passing second physical constraints information associated with repeater placement and routing in the parent macro that overlap the area of the child macro from the parent level to the child macro; adjusting the repeater placement to a nearest non-reserved location in the child macro to generate a new repeater location in the child macro; passing the new repeater location from the child macro to the parent macro; excluding an area from an abstract representation of the child macro corresponding to the new repeater location to signify that the new repeater location is not owned by the child macro; adjusting the repeater placement in the parent macro to the new repeater location; and generating a complete physical implementation of the parent macro including the repeater placement inside the area excluded from the abstract representation of the child macro. 5. A method of hierarchical repeater insertion comprising: defining an initial floorplan of parent macro in a hierarchical circuit design; passing outline and pin locations from the initial floorplan from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan of the child macro in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing first physical constraints information from the child macro to the parent macro; determining an ideal location for a repeater in the common area in response to the first physical constraints information; passing second physical constraints information associated with repeater placement and routing in the parent macro that overlap the area of the child macro from the parent level to the child macro; adjusting the repeater placement to a nearest non-reserved location in the child macro to generate a new repeater location in the child macro; passing the new repeater new location from the child macro to the parent macro; excluding an area from an abstract representation of the child macro corresponding to the new repeater location to signify that the new repeater location is not owned by the child macro; adjusting the repeater placement in the parent macro to the new repeater location; generating a complete physical implementation of the parent macro including the repeater placement inside the area excluded from the abstract representation of the child macro; and passing third physical constraints information of final detailed routing and repeaters placed in the common area from the parent macro to the child macro. 6. The method of claim 5 further comprising generating a complete physical implementation of the child macro at the child level in response to the third physical constraints information of locations of the repeaters and the final detai