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Method of forming metal fuses in CMOS processes with copper interconnect 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/82
출원번호 US-0991187 (2001-11-14)
발명자 / 주소
  • Castagnetti, Ruggero
  • Tripathi, Prabhakar Pati
  • Venkatraman, Ramnath
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Beyer Weaver & Thomas, LLP
인용정보 피인용 횟수 : 7  인용 특허 : 24

초록

The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal la

대표청구항

The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal la

이 특허에 인용된 특허 (24)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. McGrath Robert Daniel, CMOS imager with improved sensitivity.
  3. Subbanna Seshadri, CMOS structure with FETS having isolated wells with merged depletions and methods of making same.
  4. Pan Jui-Hsiang,TWX, Electrostatic discharge protection circuit.
  5. Rangappan Anikara (Torrance CA), Integrated circuit fuse link having an exothermic charge adjacent the fuse portion.
  6. Sacarisen Stephen P. (Garland TX) Blankenship Gene E. (Richardson TX) Shah Rajiv R. (Plano TX) Tran Toan (Dallas TX) Myers David J. (Dallas TX) Lin Johnson J. (Plano TX) Thompson Steve (Richmond TX), MOS programmable memories using a metal fuse link and process for making the same.
  7. Timothy Harrison Daubenspeck ; William Thomas Motsiff ; Jed Hickory Rankin, Method and structure for a semiconductor fuse.
  8. Ying Shulan,TWX ; Hung Shu-Chi,TWX, Method for etching fuse windows in IC devices and devices made.
  9. Rodriguez Robert A. ; Dopp Douglas J. ; Booth ; Jr. Robert E., Method for forming a laser alterable fuse area of a memory cell using an etch stop layer.
  10. Welch Michael T. (Sugarland TX) McMann Ronald E. (Rosenberg TX) Torreno ; Jr. Manuel L. (Houston TX) Garcia ; Jr. Evaristo (Rosenberg TX), Method of making a scalable fuse link element.
  11. Kusumi Yoshihiro,JPX ; Yokoi Takahiro,JPX ; Iida Satoshi,JPX, Method of manufacturing semiconductor device.
  12. Tze-Liang Lee TW; Mong-Song Liang TW, Method of protecting a copper pad structure during a fuse opening procedure.
  13. Aoki Masaaki (Minato JPX) Yano Kazuo (Kokubunji JPX) Masuhara Toshiaki (Nishitama JPX), Semiconductor device.
  14. Hiroshi Ikegami JP; Keiichi Sasaki JP; Nobuo Hayasaka JP, Semiconductor device.
  15. Toshifumi Minami JP, Semiconductor device and method of manufacturing the same.
  16. Lee Dong-Hun,KRX ; Ahn Jong-Hyon,KRX, Semiconductor device having a fuse.
  17. Jang-Man Ko KR, Semiconductor device having a fuse and fabricating method therefor.
  18. Nagai Nobutaka,JPX, Semiconductor device having a fuse of the laser make-link programming type.
  19. Shiratake Shigeru,JPX ; Genjo Hideki,JPX ; Ido Yasuhiro,JPX ; Hachisuka Atsushi,JPX ; Taniguchi Koji,JPX, Semiconductor device having a metallic fuse member and cutting method thereof with laser light.
  20. Ema Taiji,JPX ; Itabashi Kazuo,JPX ; Ikemasu Shinichiroh,JPX ; Mitani Junichi,JPX ; Yanagita Itsuo,JPX ; Suzuki Seiichi,JPX, Semiconductor device having triple wells.
  21. Lee Chang-Ho,KRX ; Jeon Jun-Young,KRX, Semiconductor device with a plurality of fuses.
  22. Klaasen William A. (Underhill VT) Wang Wen-Yuan (Hopewell Junction NY), Soft error immune CMOS static RAM cell.
  23. Zhang Kevin X., Soft error immunity in CMOS circuits with large shared diffusion areas.
  24. Milind Ganesh Weling ; Subhas Bothra ; Satyendra Sethi, Use of optimized film stacks for increasing absorption for laser repair of fuse links.

이 특허를 인용한 특허 (7)

  1. Liu, Yauh-Ching; Castagnetti, Ruggero; Venkatraman, Ramnath, Fuse construction for integrated circuit structure having low dielectric constant dielectric material.
  2. Chen, Fen; Gambino, Jeffrey P.; He, Zhong-Xiang; Lee, Tom C.; Malinowski, John C.; Stamper, Anthony K., Method for forming thin film resistor and terminal bond pad simultaneously.
  3. Lee,Jun Seok, Methods of fabricating semiconductor devices.
  4. Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Ching-San; Lin, Mou-Shiung, Semiconductor chip with passivation layer comprising metal interconnect and contact pads.
  5. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  6. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  7. Chen, Fen; Gambino, Jeffrey P.; He, Zhong-Xiang; Lee, Tom C.; Malinowski, John C.; Stamper, Anthony K., Semiconductor structure with thin film resistor and terminal bond pad.
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