초록 ▼

A memory cell has two diffusion areas in a substrate with a channel therebetween. The memory cell also includes a trapping dielectric layer at least over the channel, a gate at least above the trapping dielectric layer, and an implant in the substrate adapted to provide maximal band-to-band tunnelin

A memory cell has two diffusion areas in a substrate with a channel therebetween. The memory cell also includes a trapping dielectric layer at least over the channel, a gate at least above the trapping dielectric layer, and an implant in the substrate adapted to provide maximal band-to-band tunneling during erasure of charge stored in the trapping dielectric layer.

대표청구항 ▼

1. A memory cell comprising: two diffusion areas in a substrate with a channel therebetween; a trapping dielectric layer at least over said channel; a gate at least above said trapping dielectric layer; and an implant in said substrate adapted to provide maximal band-to-band tunneling during e

1. A memory cell comprising: two diffusion areas in a substrate with a channel therebetween; a trapping dielectric layer at least over said channel; a gate at least above said trapping dielectric layer; and an implant in said substrate adapted to provide maximal band-to-band tunneling during erasure of charge stored in said trapping dielectric layer. 2. A memory cell comprising: two diffusion areas in a substrate with a channel therebetween; a trapping dielectric layer at least over said channel; a gate at least above said trapping dielectric layer; and an implant in said substrate adapted to provide a maximal rate during erasure of charge stored in said trapping dielectric layer. 3. A memory cull comprising: two diffusion areas in a substrate with a channel therebetween; a trapping dielectric layer at least over said channel; a gate at least above said trapping dielectric layer; and an implant in said substrate, wherein, for an access operation, one of said diffusion areas acts as a source and the other diffusion area acts as a drain, and wherein during an erase operation said implant is adapted to provide a significantly higher lateral field in the general vicinity of the diffusion area acting as the drain than in said channel. 4. A memory cell comprising: two diffusion areas in a substrate with a channel therebetween; a trapping dielectric layer at least over said channel; a gate at least above said trapping dielectric layer; and a boron implant in said substrate, wherein during an erase operation said boron implant is adapted to enhance the injection of hot holes into said trapping dielectric layer. 5. A memory cell according to claim 4 and wherein said cell is adapted to perform tunnel assisted hot hole injection during erasure. 6. A cell according to any of claims 1-4 wherein, for 0.5 μm technology, said implant is 1-4×1013per cm2of Boron at 60 KeV, provided at 20° from the vertical. 7. A cell according to any of claims 1-4 and wherein said implant is a pocket implant. 8. A cell according to any of claims 1-4 wherein said implant provides a greater concentration of Boron near at least one of said diffusion areas than in a deep portion of said substrate. 9. A cell according to any of claims 1-4 and wherein said dielectric layer is an oxide-nitride-oxide (ONO) layer.