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Electronic component overlapping dice of unsingulated semiconductor wafer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/301
출원번호 US-0971981 (2001-10-04)
발명자 / 주소
  • Khandros, Igor Y.
  • Pedersen, David V.
  • Eldridge, Benjamin N.
  • Roy, Richard S.
  • Mathieu, Gaetan
출원인 / 주소
  • FormFactor, Inc.
대리인 / 주소
    Merkadeau, Stuart L.Burraston, N. Kenneth
인용정보 피인용 횟수 : 67  인용 특허 : 39

초록

The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provid

대표청구항

The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provid

이 특허에 인용된 특허 (39)

  1. Little Michael J. (Woodland Hills CA) Grinberg Jan (Los Angeles CA) Garvin Hugh L. (Malibu CA), 3-D integrated circuit assembly employing discrete chips.
  2. Kobayashi Mituo (Aioi JPX) Usuda Osamu (Tatsuno JPX) Sano Yoshihiko (Hyogo JPX) Atsumi Koichiro (Yokohama JPX), Apparatus and method for manufacturing semiconductor device.
  3. Ahmad Umar M. ; Atwood Eugene R., Bare die multiple dies for direct attach.
  4. Hernandez Jorge M. (Mesa AZ) Gilderdale Aleta (Chandler AZ), Decoupling capacitor for surface mounted leadless chip carriers, surface mounted leaded chip carriers and Pin Grid Array.
  5. Hunt James W. (P.O. Box 489 Edna TX 77957), Device for assembling interlocking road mat segments for temporary roads.
  6. Herandez Jorge M. (1920 E. Jarvis Mesa AZ 85202) Simpson Scott S. (Senexet Rd. Woodstock CT 06281) Hyslop Michael S. (4147 W. Victoria La. Chandler AZ 85226), Device for interconnecting integrated circuit packages to circuit boards.
  7. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  8. Yoneda Takehiko (Miyazaki JPX) Yoshimoto Masahiro (Miyazaki JPX) Takayama Yoshihiko (Miyazaki JPX) Tsujhi Tetsjhi (Miyazaki JPX) Taki Hiromitsu (Miyazaki JPX), Face-mounting type module substrate attached to base substrate face to face.
  9. Pasch Nicholas F. (Pacifica CA), Flexible preformed planar structures for interposing between a chip and a substrate.
  10. Fox ; III Angus C. (Boise ID) Farnworth Warren M. (Nampa ID), High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vi.
  11. Saito Takashi,JPX ; Tanaka Kouji,JPX, High-modulus iron-based alloy with a dispersed boride.
  12. Oki Shinichi (Osaka JPX) Nagao Koichi (Osaka JPX) Nakata Yoshiro (Kyoto JPX), Inspecting method for semiconductor devices.
  13. Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA) Fulcher Edwin (Palo Alto CA), Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies.
  14. Jeng-Jye Shau, Inter-dice wafer level signal transfer methods for integrated circuits.
  15. Philofsky, Elliott; Parkinson, Ward; Wilson, Dennis, Lead frame device including ceramic encapsulated capacitor and IC chip.
  16. Degani Yinon ; Dudderar Thomas Dixon ; Tai King Lien, Method for assembling multichip modules.
  17. Malladi Deviprasad ; Ansari Shahid S. ; Bogatin Eric, Method for direct attachment of an on-chip bypass capacitor in an integrated circuit.
  18. Vindasius Alfons ; Sautter Kenneth M., Method for forming vertical interconnect process for silicon segments with dielectric isolation.
  19. Devereaux Kevin M. (Boise ID) Bunn Mark (Boise ID) Higgins Brian (Boise ID), Method of testing individual dies on semiconductor wafers prior to singulation.
  20. Pfizenmayer Henry L. (Phoenix AZ), Mount for supporting a high frequency transformer in a hybrid module.
  21. Tower John R. (West Deptford NJ), Multi-chip imager.
  22. Rostoker Michael D. (San Jose CA), Multi-chip semiconductor arrangements using flip chip dies.
  23. Mori Syuji,JPX ; Sekiba Takasi,JPX ; Kudo Osamu,JPX, Multi-chip semiconductor chip module.
  24. Tuckerman David B. (Dublin CA), Multichip module having SiO2 insulating layer.
  25. Fujita Suguru (Tokyo JPX) Takahashi Kazuaki (Kawasaki JPX) Sagawa Morikazu (Tama JPX) Sakai Hiroyuki (Katano JPX) Ota Yorito (Kobe JPX) Inoue Kaoru (Kadoma JPX), Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps.
  26. Gupta Debabrata (Scottsdale AZ) Drye James E. (Mesa AZ), Multiple integrated circuit module which simplifies handling and testing.
  27. Pai Deepak K. (Burnsville MN) Krinke Terrance A. (Roseville MN), Plated compliant lead.
  28. Chang Sung Chul ; Khandros Igor Y. ; Smith William D., Process of mounting spring contacts to semiconductor devices.
  29. Blanton James A. (Kokomo IN), Provision of substrate pillars to maintain chip standoff.
  30. Ahmad Aftab (Boise ID) Weber Larren G. (Caldwell ID) Green Robert S. (Boise ID), Semiconductor array having built-in test circuit for wafer level testing.
  31. Otsuka Kanji (Higashiyamato JPX) Kato Masao (Hadano JPX) Kumagai Takashi (Isehara JPX) Usami Mitsuo (Ohme JPX) Kuroda Shigeo (Ohme JPX) Sahara Kunizo (Nishitama JPX) Yamada Takeo (Koganei JPX) Miyamo, Semiconductor device having leads for mounting to a surface of a printed circuit board.
  32. Adachi Chinatsu (Minou JPX) Nishijima Masaaki (Moriguchi JPX) Ota Yorito (Kobe JPX) Ishikawa Osamu (Kyoto JPX), Semiconductor device including a first chip having an active element and a second chip having a passive element.
  33. Chitranjan N. Reddy, Semiconductor devices having cooperative mode option at assembly stage and method thereof.
  34. Yamamoto Kazumichi (Hachioji JPX) Nakanishi Keiichirou (Tokyo PA JPX) Yasunaga Moritoshi (Pittsburgh PA) Saitoh Tatsuya (Kokubunji JPX) Shibata Katsunari (Kokubunji JPX) Yamada Minoru (Hanno JPX) Mas, Semiconductor integrated circuit device and computer system using the same.
  35. Purdom Gregory W. ; Berecz Endre M., Stacked memory for flight recorders.
  36. Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA), Testing and exercising individual, unsingulated dies on a wafer.
  37. Beaman Brian S. (Hyde Park NY) Doany Fuad E. (Katonah NY) Fogel Keith E. (Bardonia NY) Hedrick ; Jr. James L. (Oakland CA) Lauro Paul A. (Nanuet NY) Norcott Maurice H. (Valley Cottage NY) Ritsko John, Three dimensional high performance interconnection package.
  38. Zavracky Paul M. ; Zavracky Matthew ; Vu Duy-Phach ; Dingle Brenda, Three dimensional processor using transferred thin film circuits.
  39. Tatematsu Takeo (Yokohama JPX), Wafer scale integration device with dummy chips and relay pads.

이 특허를 인용한 특허 (67)

  1. Strid, Eric; Gleason, K. Reed, Active wafer probe.
  2. Strid,Eric; Gleason,K. Reed, Active wafer probe.
  3. Strid, Eric; Campbell, Richard, Calibration structures for differential signal probing.
  4. Campbell, Richard; Strid, Eric W.; Andrews, Mike, Differential signal probe with integral balun.
  5. Strid, Eric; Campbell, Richard, Differential signal probing system.
  6. Campbell, Richard L.; Andrews, Michael, Differential waveguide probe.
  7. Burcham, Terry; McCann, Peter; Jones, Rod, Double sided probing structures.
  8. Burcham,Terry; McCann,Peter; Jones,Rod, Double sided probing structures.
  9. Larsen,Jelena H.; Fong,Chee Kiong; Atkinson,Peter Anthony; Rodriguez Montanez,Raul, High density surface mount part array layout and assembly technique.
  10. Eldridge, Benjamin N., Interconnect assemblies and methods.
  11. Eldridge, Benjamin N., Interconnect assemblies and methods.
  12. Eldridge,Benjamin N., Interconnect assemblies and methods.
  13. Andrews, Peter; Hess, David; New, Robert, Interface for testing semiconductors.
  14. Tervo,Paul A.; Cowan,Clarence E., Low-current pogo probe card.
  15. Tervo,Paul A.; Cowan,Clarence E., Low-current pogo probe card.
  16. Schwindt,Randy J., Low-current probe card.
  17. Rabadam, Eleanor P.; Foehringer, Richard B., Lower profile package with power supply in package.
  18. Gleason, K. Reed; Bayne, Michael A.; Smith, Kenneth; Lesher, Timothy; Koxxy, Martin, Membrane probing method using improved contact.
  19. Gleason, Reed; Bayne, Michael A.; Smith, Kenneth; Lesher, Timothy; Koxxy, Martin, Membrane probing method using improved contact.
  20. Gleason, K. Reed; Smith, Kenneth R.; Bayne, Mike, Membrane probing structure with laterally scrubbing contacts.
  21. Gleason, Reed; Bayne, Michael A.; Smith, Kenneth; Lesher, Timothy; Koxxy, Martin, Membrane probing system.
  22. Gleason,Reed; Bayne,Michael A.; Smith,Kenneth; Lesher,Timothy; Koxxy,Martin, Membrane probing system.
  23. Gleason,Reed; Bayne,Michael A.; Smith,Kenneth; Lesher,Timothy; Koxxy,Martin, Membrane probing system.
  24. Smith,Kenneth; Gleason,Reed, Membrane probing system.
  25. Smith,Kenneth; Gleason,Reed, Membrane probing system.
  26. Tervo,Paul A.; Smith,Kenneth R.; Cowan,Clarence E.; Dauphinais,Mike P.; Koxxy,Martin J., Membrane probing system.
  27. Tervo,Paul A.; Smith,Kenneth R.; Cowan,Clarence E.; Dauphinais,Mike P.; Koxxy,Martin J., Membrane probing system.
  28. Gleason, K. Reed; Smith, Kenneth R.; Bayne, Mike, Membrane probing system with local contact scrub.
  29. Gleason,K. Reed; Smith,Kenneth R.; Bayne,Mike, Membrane probing system with local contact scrub.
  30. Goto,Yuichi; Hosomi,Eiichi, Method and system for a pad structure for use with a semiconductor package.
  31. Gleason,Reed; Bayne,Michael A.; Smith,Kenneth, Method for constructing a membrane probe using a depression.
  32. Hayden, Leonard; Martin, John; Andrews, Mike, Method of assembling a wafer probe.
  33. Gleason, Reed; Bayne, Michael A.; Smith, Kenneth, Method of constructing a membrane probe.
  34. Smith, Kenneth R., Method of replacing an existing contact of a wafer probing assembly.
  35. Roberts, Brent M.; Roy, Mihir K.; Srinivasan, Sriram; Narasimhan, Sridhar, Microelectronic package and method for a compression-based mid-level interconnect.
  36. Roberts, Brent M.; Roy, Mihir K.; Sriniyasan, Sriram; Narasimhan, Sridhar, Microelectronic package and method for a compression-based mid-level interconnect.
  37. Strid,Eric; Campbell,Richard, On-wafer test structures for differential signals.
  38. Tervo,Paul A.; Cowan,Clarence E., POGO probe card for low current measurements.
  39. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.
  40. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.
  41. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.
  42. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.
  43. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.
  44. Campbell,Richard L.; Andrews,Michael; Bui,Lynh, Probe for high frequency signals.
  45. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Probe for testing a device under test.
  46. Smith, Kenneth; Jolley, Michael; Van Syckel, Victoria, Probe head having a membrane suspended probe.
  47. Smith,Kenneth; Jolley,Michael; Van Syckel,Victoria, Probe head having a membrane suspended probe.
  48. Schwindt,Randy, Probe holder for testing of a test device.
  49. Smith, Kenneth R.; Hayward, Roger, Probing apparatus with impedance optimized interface.
  50. Smith, Kenneth R., Replaceable coupon for a probing apparatus.
  51. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Shielded probe for high-frequency testing of a device under test.
  52. Gleason, K. Reed; Lesher, Tim; Strid, Eric W.; Andrews, Mike; Martin, John; Dunklee, John; Hayden, Leonard; Safwat, Amr M. E., Shielded probe for testing a device under test.
  53. Gleason,K. Reed; Lesher,Tim; Andrews,Mike; Martin,John, Shielded probe for testing a device under test.
  54. Gleason,K. Reed; Lesher,Tim; Andrews,Mike; Martin,John, Shielded probe for testing a device under test.
  55. Gleason,K. Reed; Lesher,Tim; Andrews,Mike; Martin,John, Shielded probe for testing a device under test.
  56. Gleason,K. Reed; Lesher,Tim; Andrews,Mike; Martin,John, Shielded probe for testing a device under test.
  57. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Shielded probe for testing a device under test.
  58. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Shielded probe for testing a device under test.
  59. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Shielded probe with low contact resistance for testing a device under test.
  60. Andrews, Peter; Hess, David, System for testing semiconductors.
  61. Campbell, Richard, Test structure and probe for differential signals.
  62. Campbell,Richard, Test structure and probe for differential signals.
  63. Hayden, Leonard; Martin, John; Andrews, Mike, Wafer probe.
  64. Hayden,Leonard; Martin,John; Andrews,Mike, Wafer probe.
  65. Hayden,Leonard; Martin,John; Andrews,Mike, Wafer probe.
  66. Hayden,Leonard; Martin,John; Andrews,Mike, Wafer probe.
  67. Campbell, Richard, Wideband active-passive differential signal probe.
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