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A method of controlling a permanent magnet turbogenerator/motor includes providing a protected load connected in parallel with the turbogenerator/motor through a pulse width modulated inverter configured in a first operating mode to supply controlled current from the turbogenerator/motor to a utilit

A method of controlling a permanent magnet turbogenerator/motor includes providing a protected load connected in parallel with the turbogenerator/motor through a pulse width modulated inverter configured in a first operating mode to supply controlled current from the turbogenerator/motor to a utility electrical power source, and selectively connected to the utility electrical power source through an isolation device, monitoring the utility electrical power source, and automatically disconnecting the protected load from the utility electrical power source while reconfiguring the pulse width modulated inverter in a second operating mode to supply controlled voltage to the protected load when a fault is detected in the utility electrical power source. The present invention provides an external or integrated dual mode controller which can be used to provide automatic transitions of a turbogenerator/motor between grid-connected modes where a PWM inverter provides a controlled AC current source to stand-alone modes where the PWM inverter provides a controlled AC voltage source to a protected load. Three phase rotation sequence can be set to positive or negative rotation, or be set to the last measured rotation for the utility grid to enable automatic transitions from stand-alone to grid-connect modes. In addition, the present invention provides for detecting a reference phase angle of the three-phase power provided by a utility grid such that gradual synchronization/resynchronization of a protected parallel connected load can be performed by appropriately controlling the PWM inverter prior to re-connection to the utility grid.

대표청구항 ▼

A method of controlling a permanent magnet turbogenerator/motor includes providing a protected load connected in parallel with the turbogenerator/motor through a pulse width modulated inverter configured in a first operating mode to supply controlled current from the turbogenerator/motor to a utilit

A method of controlling a permanent magnet turbogenerator/motor includes providing a protected load connected in parallel with the turbogenerator/motor through a pulse width modulated inverter configured in a first operating mode to supply controlled current from the turbogenerator/motor to a utility electrical power source, and selectively connected to the utility electrical power source through an isolation device, monitoring the utility electrical power source, and automatically disconnecting the protected load from the utility electrical power source while reconfiguring the pulse width modulated inverter in a second operating mode to supply controlled voltage to the protected load when a fault is detected in the utility electrical power source. The present invention provides an external or integrated dual mode controller which can be used to provide automatic transitions of a turbogenerator/motor between grid-connected modes where a PWM inverter provides a controlled AC current source to stand-alone modes where the PWM inverter provides a controlled AC voltage source to a protected load. Three phase rotation sequence can be set to positive or negative rotation, or be set to the last measured rotation for the utility grid to enable automatic transitions from stand-alone to grid-connect modes. In addition, the present invention provides for detecting a reference phase angle of the three-phase power provided by a utility grid such that gradual synchronization/resynchronization of a protected parallel connected load can be performed by appropriately controlling the PWM inverter prior to re-connection to the utility grid. d interconnections and disposed in a region spaced from said interconnections; and an insulating film covering said interconnections and dummy interconnections, said insulating film including a film planarized by polishing. 5. A device according to claim 1, wherein said dummy gate interconnections are formed also in a scribing area. 6. A device according to claim 1, wherein each gate electrode constitutes a gate electrode of a selective MISFET of a memory cell of a DRAM. 7. A semiconductor integrated circuit device according to claim 1, wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions. 8. A semiconductor integrated circuit device comprising: an active region and a dummy region of a semiconductor substrate; a semiconductor element formed in said active region; a trench defining said active region and said dummy region; an element isolation insulating film embedded in said trench with an insulating film including a film planarized by polishing; and a gate interconnection formed on said active region and element isolation insulating film; and an element isolation region defining said active region and being comprised of said dummy region and element isolation insulating film, said gate interconnection extending over said element isolation insulating film so as not to extend over said dummy region. 9. A device according to claim 8, wherein: a dummy gate interconnection is comprised of a same layer as said gate interconnection, and said dummy gate interconnection is disposed on said dummy region and element isolation insulating film in said element isolation region. 10. A device according to claim 8, wherein said dummy region is formed also in a scribing area. 11. A semiconductor integrated circuit device according to claim 8, wherein dummy gate interconnections are comprised of a same layer as said gate interconnection and are formed over said element isolation region. 12. A semiconductor integrated circuit device comprising: interconnections formed on a principal surface of a semiconductor substrate; dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections; and an insulating film covering said interconnections and dummy interconnections and including a film planarized by polishing; said dummy interconnections being formed also in a scribing area, wherein a length of said dummy interconnection is shorter than a distance between bonding pads. 13. A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface, said principal surface including active areas for MISFETs to be formed and an isolation area for providing a required space between said active areas; a trench pattern formed in said substrate except for said active areas such that a plurality of dummy semiconductor regions separated from each other by said trench pattern are formed at said isolation area, said trench pattern having a selected trench portion and another trench portion, said selected trench portion formed in a portion of said isolation area where a gate interconnection for said elements is to be provided, and said another trench portion formed so as to define active semiconductor regions at said active areas; a first insulating film buried in said trench pattern and formed by polishing an insulating film deposited on said principal surface having said trench pattern; gate insulating films of said MISFETs formed on said active semiconductor regions; gate electrodes of said MISFETs formed on said gate insulating films and formed integrally with said gate interconnections, said gate interconnections electrically coupled between said MISFETs and extending over said selected trench portion; dummy interconnections formed with a same level layer