초록 ▼

A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a nu

A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL.

대표청구항 ▼

A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a nu

A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL. rnhard E. et al., Surface Micromachined Accelerometers, IEEE J. of Solid-State Circuits, v. 31 (3) 366-375, Mar. 1996. Fedder, Gary K. et al., Multimode Digital Control of a Suspended Polysilicon Microstructure, J. of Microelectromechanical Sys., V. 5 (4) 283-297, Dec. 1996. Noriega, Gerardo, Sigma-Delta A/D Converters-Audio and Medium Bandwidths, Technical Notes-DT3 from RMS Instruments website: www.rmsinst.com, 6 pages, Feb. 1996. Internet page: Decimator Filter DLL, NeuroDimension Inc.: www.nd.com , May 31, 2001. U.S. patent application Ser. No.: 09/406,654, filed on Sep. 27, 1999. U.S. patent application Ser. No.: 09/400,125, filed on Sep. 21, 1999. U.S. patent application Ser. No.: 09/406,509, filed on Sep. 28, 1999. U.S. patent application Ser. No.: 09/955,493, filed on Sep. 18, 2001. U.S. patent application Ser. No.: 09/955,494, filed on Sep. 18, 2001. U.S. patent application Ser. No.: 09/675,861, filed on Sep. 29, 2000. Storment, C.W., et al. "Flexible, Dry-Released Process for Aluminum Electrostatic Actuators." Journal of Microelectromechanical Systems, 3(3), Sep. 1994, pp. 90-96.