초록 ▼

A surface imaging radar system for an airborne platform, the system comprises a transmitter for generating a radar signal. The system also comprises an antenna configured to transmit a radar signal generated by the transmitter and receive radar return information from one or more directions directly

A surface imaging radar system for an airborne platform, the system comprises a transmitter for generating a radar signal. The system also comprises an antenna configured to transmit a radar signal generated by the transmitter and receive radar return information from one or more directions directly below the airborne platform to an angular direction of approximately 30 degrees greater than straight down. The system also includes a processor configured to generate surface information based on the received radar return information and an image processor for generating an image based on the surface information.

대표청구항 ▼

A surface imaging radar system for an airborne platform, the system comprises a transmitter for generating a radar signal. The system also comprises an antenna configured to transmit a radar signal generated by the transmitter and receive radar return information from one or more directions directly

A surface imaging radar system for an airborne platform, the system comprises a transmitter for generating a radar signal. The system also comprises an antenna configured to transmit a radar signal generated by the transmitter and receive radar return information from one or more directions directly below the airborne platform to an angular direction of approximately 30 degrees greater than straight down. The system also includes a processor configured to generate surface information based on the received radar return information and an image processor for generating an image based on the surface information. ion and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a channel region below the gate structure and extending between the first and the second lightly doped regions; a junction between the source region and the first lightly doped region having a first grading of dopant concentration; a junction between the first lightly doped region and the channel region having a second grading of dopant concentration; a junction between the channel region and the second lightly doped region having a third grading of dopant concentration; and a junction between the second lightly doped region and the drain region having a fourth grading of dopant concentration. 2. The MOSFET of claim 1, wherein each of the first and second sidewall structures comprises a layer of oxide and an insulating layer extending solely over the layer of oxide. 3. The MOSFET of claim 2, wherein each of the first implanted region and the second implanted region comprises a low dosage phosphorous implant. 4. The MOSFET of claim 2, wherein each of the third implanted region and the fourth implanted region comprises a boron implant. 5. The MOSFET of claim 1, wherein the gate structure comprises an oxide layer, a polysilicon layer, a tungsten silicide layer and a nitride layer. 6. The MOSFET of claim 1, wherein each of the drain region and the source region comprises a lightly doped region and a heavily doped region. 7. The MOSFET of claim 6, wherein the lightly doped region within each of the drain region and the source region comprises a low dosage arsenic implant. 8. The MOSFET of claim 6, wherein the heavily doped region within each of the drain region and the source region comprises a high dosage arsenic implant. 9. The MOSFET of claim 1, wherein the first and second lightly doped regions comprise low dosage arsenic LDD regions. 10. The MOSFET of claim 1, wherein the graded junctions comprise low dosage phosphorous implants. 11. A MOSFET formed on a substrate having a surface comprising: a source region and a drain region below said surface; a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure; a first lightly doped region located solely below the first sidewall structure and adjacent to but not substantially extending into and under the source region; a second lightly doped region located solely below the second sidewall structure and adjacent to but not substantially extending into and under the drain region; a first implanted region extending below the source region and the first lightly doped region; a second implanted region extending below the drain region and the second lightly doped region; a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively; a channel region below the gate structure and extending between the first and the second lightly doped regions; and a plurality of junctions between each of the source region and the first lightly doped region, the first lightly doped region and the channel region, the channel region and the second lightly doped region and the second lightly doped region and the drain region, each junction including a grading of dopant concentration. 12. The MOSFET of claim 11, wherein the first and second lightly doped regions comprise low dosage arsenic LDD regions. 13. The MOSFET of claim 11, wherein the graded junctions comprise low dosage phosphorous implants. 14. A MOSFET on a substrate having a source region and a drain region, the MOSFET comprising: at least one lightly doped region located adjacent at least one of the source region and the drain region but not substantially extending thereinto and thereunder, the at least one lightly doped region comprising a low dosage; a first implanted region extending below the source region; a second implante