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A computing system including a plurality of data processing systems and a peripheral input device. The peripheral input device includes a computer selector for selecting one of the plurality of data processing systems for interaction with the peripheral input device. The peripheral input device also

A computing system including a plurality of data processing systems and a peripheral input device. The peripheral input device includes a computer selector for selecting one of the plurality of data processing systems for interaction with the peripheral input device. The peripheral input device also includes a wireless transmitter for providing communications with any one of the plurality of data processing systems. Each of the plurality of data processing systems includes a wireless receiver for receiving wireless communications from the peripheral input device.

대표청구항 ▼

A computing system including a plurality of data processing systems and a peripheral input device. The peripheral input device includes a computer selector for selecting one of the plurality of data processing systems for interaction with the peripheral input device. The peripheral input device also

A computing system including a plurality of data processing systems and a peripheral input device. The peripheral input device includes a computer selector for selecting one of the plurality of data processing systems for interaction with the peripheral input device. The peripheral input device also includes a wireless transmitter for providing communications with any one of the plurality of data processing systems. Each of the plurality of data processing systems includes a wireless receiver for receiving wireless communications from the peripheral input device. wherein the instructing step includes fixing the impedance of a programmable load, the programmable load being a portion of the integrated circuit. 10. A method according to claim 7, wherein the operating step further comprises: storing values in the integrated circuit to define a multiplication factor of the phase lock loop; and outputting the values to the phase lock loop. 11. A method according to claim 4, wherein the impedance is a capacitance. 12. A timing circuit comprising: a programmable load circuit adapted to be coupled to a crystal to receive a source frequency; an oscillator circuit adapted to be coupled to receive said source frequency; a frequency multiplier circuit coupled to said oscillator circuit to receive said source frequency; and a programming circuit configured to supply stored first programming data to said programmable load circuit to adjust said source frequency and stored second programming data to said frequency multiplier circuit, such that said frequency multiplier circuit supplies an output frequency which is substantially equal to a product of said adjusted source frequency and a multiplication factor designated by said second programming data. 13. A timing circuit in accordance with claim 12, wherein said programmable load circuit is a programmable capacitive load circuit. 14. A timing circuit in accordance with claim 13, wherein said source frequency is adapted to be supplied over a source frequency line adapted to be coupled to said crystal, said programmable capacitive load circuit comprises: a plurality of capacitors, selected ones of said plurality of capacitors being coupled to said source frequency line. 15. A timing circuit in accordance with claim 14, wherein said programmable capacitive load circuit further comprises: a plurality of switching elements, each of which having a first terminal connected in common to said source frequency line, and a second terminal coupled to a corresponding one of said plurality of capacitors. 16. A timing circuit in accordance with claim 15, wherein said programming circuit generates a plurality of output signals in accordance with said first programming data stored therein, said plurality of output signals being supplied to said programmable capacitive load circuit to activate selected ones of said plurality of switching elements to connect corresponding ones of said capacitors to said source frequency line. 17. A timing circuit in accordance with claim 15, wherein each of said plurality of switching elements comprises a MOS transistor. 18. A timing circuit in accordance with claim 12, wherein said frequency multiplier circuit includes a phase locked loop circuit. 19. A timing circuit in accordance with claim 12, wherein said second programming data comprises a first parameter P and a second parameter Q, said output frequency (Fout) and said adjusted source frequency (Fadj) satisfying: Fout=Fadj(P/Q). 20. A timing circuit in accordance with claim 19, wherein said frequency multiplier loop circuit comprises: a first divider for dividing said adjusted source frequency by a first parameter of said second programming data to generate a first frequency; a second divider included in said phase locked loop circuit for dividing said output frequency by a second parameter of said second programming data for generating a second frequency; and a detector included in said phase locked loop circuit and coupled for receiving said first and second frequencies, said detector outputting a control signal in response to said first and second frequencies for controlling a generation of said output frequency. 21. A timing circuit in accordance with claim 20, further comprising: a third divider circuit, coupled to an output of said phase locked loop circuit and said programming circuit, for dividing said output frequency by a third parameter of said second programming data stored in said programm