초록 ▼

This invention discloses a method for managing a computer network connected to the Internet through a network connection, such as different Internet Service Providers, including the steps of; sending polling requests through a plurality of routes from a computer network to a remote server computer,

This invention discloses a method for managing a computer network connected to the Internet through a network connection, such as different Internet Service Providers, including the steps of; sending polling requests through a plurality of routes from a computer network to a remote server computer, receiving replies from the remote server computer corresponding to the polling requests, and measuring proximities of the remote server computer to the computer network based on the received replies.

대표청구항 ▼

This invention discloses a method for managing a computer network connected to the Internet through a network connection, such as different Internet Service Providers, including the steps of; sending polling requests through a plurality of routes from a computer network to a remote server computer,

This invention discloses a method for managing a computer network connected to the Internet through a network connection, such as different Internet Service Providers, including the steps of; sending polling requests through a plurality of routes from a computer network to a remote server computer, receiving replies from the remote server computer corresponding to the polling requests, and measuring proximities of the remote server computer to the computer network based on the received replies. rises a lower significant bit than said corresponding partial all-one evaluator input signal bit; wherein if an increment operating is performed, said complement input signal bit is selected if all lower significant input signal bits of said input signal bit have a logical "1" value and said input signal bit is selected if any of said lower significant input signal bits of said input signal bit have a logical "0" value. 2. A circuit in accordance with claim 1, wherein: each of said plurality of group all-one evaluators comprises a logical AND gate coupled to receive each of said successively significant bits of said input signal that are in said corresponding mutually-exclusive grouping; and each of said plurality of partial all-one evaluators comprise a logical AND gate coupled to receive each of said outputs of said corresponding group all-one evaluators and each of said corresponding lower significant bits that are not included in one of said groupings of said lower significant group all-one evaluators. 3. A circuit in accordance with claim 1, wherein: each of said plurality of group all-one evaluators comprises a logical NOR gate coupled to receive complements of each of said successively significant bits of said input signal that are in said corresponding mutually-exclusive grouping; and each of said plurality of partial all-one evaluators comprise a logical NOR gate coupled to receive complements of each of said outputs of said corresponding group all-one evaluators and complements of each of said corresponding lower significant bits that are not included in one of said groupings of said lower significant group all-one evaluators. 4. A circuit in accordance with claim 1, wherein said n-bit signal comprises a two's-complement number comprising an (n-1)-bit value and a sign bit, and an overflow condition is indicated if all input signal bits in said (n-1)-bit value have a logical "1" value and the sign bit indicates that said two's-complement number is positive. 5. A circuit in accordance with claim 4, wherein: each of said plurality of group all-one evaluators comprises a logical AND gate coupled to receive each of said successively significant bits of said input signal that are in said corresponding mutually-exclusive grouping; and each of said plurality of partial all-one evaluators comprise a logical AND gate coupled to receive each of said outputs of said corresponding group all-one evaluators and each of said corresponding lower significant bits that are not included in one of said groupings of said lower significant group all-one evaluators. 6. A circuit in accordance with claim 4, wherein: each of said plurality of group all-one evaluators comprises a logical NOR gate coupled to receive complements of each of said successively significant bits of said input signal that are in said corresponding mutually-exclusive grouping; and each of said plurality of partial all-one evaluators comprise a logical NOR gate coupled to receive complements of each of said outputs of said corresponding group all-one evaluators and complements of each of said corresponding lower significant bits that are not included in one of said groupings of said lower significant group all-one evaluators. 7. A circuit in capacitive coupling with claim 1, wherein: wherein if a decrement operation is performed, said complement input signal bit is selected if all lower significant input signal bits of said input signal bit not including the sign bit have a logical "0" value and said input signal bit is selected if any of said lower significant input signal bits of said input signal bit not including the sign bit have a logical "1" value. 8. A circuit in accordance with claim 7, wherein: said selection circuit comprises: a plurality of group all-zero evaluators, each corresponding to a mutually-exclusive grouping of successively significant bits of said input signal, and each determining and indicating via a corresp