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Group shifting and level shifting rotational arbiter system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
출원번호 US-0677035 (2000-09-29)
발명자 / 주소
  • Dotson, Gary Dan
출원인 / 주소
  • Rockwell Automation Technologies, Inc.
대리인 / 주소
    Foley & Lardner
인용정보 피인용 횟수 : 36  인용 특허 : 33

초록

An arbiter system comprises a plurality of hardware resources, a common resource, and an arbiter. The plurality of hardware resources are divided into groups of hardware resources and are coupled to the common resource and the arbiter. The arbiter controls which of the plurality of hardware resource

대표청구항

An arbiter system comprises a plurality of hardware resources, a common resource, and an arbiter. The plurality of hardware resources are divided into groups of hardware resources and are coupled to the common resource and the arbiter. The arbiter controls which of the plurality of hardware resource

이 특허에 인용된 특허 (33)

  1. Chen Ray (Folsom CA) Rabe Jeffrey L. (Gold River CA), Arbiter and arbitration process for a dynamic and flexible prioritization.
  2. Chen Jawji, Arbitration method and circuit to increase access without increasing latency.
  3. Popat Kaushik L. (Pleasanton CA), Arrangement and method of arbitration for a resource with shared user request signals and dynamic priority assignment.
  4. Pham Thai H., Cascaded round robin request selection method and apparatus.
  5. Sze Hung Y., Circuit and method for rapid checking of error correction codes using cyclic redundancy check.
  6. Davis Charles L. (Flower Mound TX) Sanders Jerry R. (Dallas TX) Rench James A. (Grand Prairie TX), Circuit combining functions of cyclic redundancy check code and pseudo-random number generators.
  7. Miyazaki Takeshi (Ohme JPX), Communication control system.
  8. Miyazaki Takeshi (Ohme JPX), Communication control system.
  9. Bowes Michael J. (Cupertino CA) Childers Brian A. (Santa Clara CA), DMA controller having a plurality of DMA channels each having multiple register sets storing different information contr.
  10. Earnest Tim ; Sonnek Chris, DMA controller with response message and receive frame action tables.
  11. Farrell Joseph K. (Boca Raton FL) Gordon Jeffrey S. (Centreville VA) Kuhl Daniel C. (Delray Beach FL) Lee Timothy V. (Boca Raton FL) Parker Tony E. (Boca Raton FL), Data link controller with channels selectively allocatable to hyper channels and hyper channel data funneled through ref.
  12. Sato Fumitaka (Tokyo JPX), Data processing system with error correction.
  13. McKinney Steven J. (Coral Springs FL) Earnshaw William E. (N. Lauderdale FL), Dual rotating priority arbitration method for a multiprocessor memory bus.
  14. Larson Mikiel L. (St Charles IL) Wilcox Wayne R. (Naperville IL), Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction.
  15. Hayek George (Chandler AZ), Global serial channel for microcontroller.
  16. Wanner Christopher C. ; Stevens Jeffrey C. ; Lester Robert A. ; Riley Dwight D. ; Maguire David J. ; Edwards James, Interfacing direct memory access devices to a non-ISA bus.
  17. Iyer Venkatraman (Sunnyvale CA) Lee Gil S. (San Jose CA), Linear feedback shift register for circuit design technology validation.
  18. Oprescu Florin (Sunnyvale CA) Teener Michael D. (Santa Cruz CA), Method and apparatus for a dynamic, multi-speed bus architecture having a scalable interface.
  19. Priem Curtis ; Rosenthal David S. H. ; Iwamoto Rick, Method and apparatus for accelerating the transfer of graphical images.
  20. Yoshida Osamu,JPX, Method and apparatus for verifying data transfer in data processor equipped with external recording unit.
  21. Graham Randolph H. (Fremont CA) Peterson Bruce R. (San Jose CA) Blackborow Richard J. (Cupertino CA), Microprocessor controlled rigid disk file subsystem.
  22. Harrison Joel N. (Monte Sereno CA) Moon William G. (Sunnyvale CA) Graham Randolph H. (Fremont CA), Modular unitary disk file subsystem.
  23. Creedon Tadhg,IEX ; Gahan Richard A.,IEX ; Morgan Fearghal,IEX, Multi-level round robin arbitration system.
  24. Oskouy Rasoul M. ; Lyon Tom ; Kashyap Prakash, Multi-virtual DMA channels, multi-bandwidth groups, host based cellification and reassembly, and asynchronous transfer mode network interface.
  25. Pezzi Louis D. (Freehold Township ; Monmouth County NJ), Multilevel priority arbiter.
  26. Gehman Judy M., Priority arbiter with shifting sequential priority scheme.
  27. Iguma Junichi (Hadano JPX), Priority control apparatus for a bus in a bus control system having input/output devices.
  28. Barnaby Michael J. ; Mammen Abe, Priority encoding and decoding for memory architecture.
  29. Grandmaison John P. (Hampton NH) Huettner Robert E. (Acton MA) Vernon John H. (Milford MA) Yu Kin C. (Burlington MA), Process and apparatus employing microprogrammed control commands for transferring information between a control processo.
  30. McSpadden Jeff R. (Isanti MN), Programmable polynomial generator.
  31. Tod D. Wolf, Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder.
  32. Ostrowski Carl L. (3194 Sunnywood Ann Arbor MI 48103), SCSI bus capacity expansion controller using gating circuits to arbitrate DMA requests from a plurality of disk drives.
  33. Lee Kuo-Chu (Franklin NJ), Tree structured variable priority arbitration implementing a round-robin scheduling policy.

이 특허를 인용한 특허 (36)

  1. Ichimiya, Junji; Kinoshita, Takayuki; Itozawa, Shintarou, Arbiter, crossbar, request selection method and information processing device.
  2. Jensen, Michael Gottlieb, Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor.
  3. Jensen,Michael Gottlieb, Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor.
  4. Kato, Tetsuya, Bus arbiter and bus access arbitrating method.
  5. Catherwood, Michael I.; Desai, Ashish, Data space arbiter.
  6. Ambroladze, Ekaterina M.; Dunn Berger, Deanna Postles; Orf, Diana Lynn; Sonnelitter, III, Robert J., Dynamic multi-level cache including resource access fairness scheme.
  7. Jensen,Michael Gottlieb; Banerjee,Soumya, Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor.
  8. Inoue,Keisuke; Iwamoto,Tatsuya, IO direct memory access system and method.
  9. Jensen, Michael Gottlieb, Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor.
  10. Jones, Darren M.; Kinter, Ryan C.; Uhler, G. Michael; Vishin, Sanjay, Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions.
  11. Prasadh, Ramamoorthy Guru, Integrated circuit having a bus network, and method for the integrated circuit.
  12. Prasadh, Ramamoorthy Guru, Integrated circuit having a bus network, and method for the integrated circuit.
  13. Jones, Darren M.; Kinter, Ryan C.; Kissell, Kevin D.; Petersen, Thomas A., Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler.
  14. Matsuyama,Hideki, Interrupt controlling circuit.
  15. Jones, Darren M.; Kinter, Ryan C.; Petersen, Thomas A.; Vishin, Sanjay, Leaky-bucket thread scheduler in a multithreading microprocessor.
  16. Hellwig,Frank; K��nig,Dietmar, Method and apparatus for allocating bus access rights in multimaster bus systems.
  17. Van Lieshout, Gert Jan; Kim, Soeng-Hun; Baghel, Sudhir Kumar; Manepalli, Venkateswara Rao, Method and apparatus for handling in-device co-existence interference in a user equipment.
  18. Inoue, Keisuke; Yasue, Masahiro, Micro interrupt handler.
  19. Chaudhari,Sunil C.; Liu,Jonathan W.; Patel,Manan; Duresky,Nicholas E., Multilevel fair priority round robin arbiter.
  20. Jensen, Michael Gottlieb; Kinter, Ryan C., Multithreading instruction scheduler employing thread group priorities.
  21. Jensen, Michael Gottlieb; Kinter, Ryan C., Multithreading instruction scheduler employing thread group priorities.
  22. Jensen, Michael Gottlieb; Jones, Darren M.; Kinter, Ryan C.; Vishin, Sanjay, Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency.
  23. Jones, Darren M.; Kinter, Ryan C.; Jensen, Michael Gottlieb; Vishin, Sanjay, Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency.
  24. Fukunaga, Hideyo; Sumou, Takeshi; Noguchi, Tsutomu; Imamura, Katsumi, Packet relaying apparatus and packet relaying method.
  25. Jensen, Michael Gottlieb; Jones, Darren M.; Kinter, Ryan C.; Vishin, Sanjay, Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages.
  26. Jensen,Michael Gottlieb, Return data selector employing barrel-incrementer-based round-robin apparatus.
  27. Subramanian,Sridhar P.; Keller,James B.; Yiu,George Kong; Wadhawan,Ruchi, Segmented interconnect for connecting multiple agents in a system.
  28. Sumou, Takeshi; Imamura, Katsumi; Fukunaga, Hideyo, Selection circuit and packet processing apparatus.
  29. Bekiares, Tyrone D; Logalbo, Bob; Miller, Trent J., Spatial quality of service prioritization algorithm in wireless networks.
  30. Yasue,Masahiro; Inoue,Keisuke, System and method of interrupt handling.
  31. Rhine,Scott Alan, Systems and methods for facilitating fair and efficient scheduling of processes among multiple resources in a computer system.
  32. Banerjee, Soumya; Jensen, Michael Gottlieb, Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states.
  33. Laughton, Arthur, Transaction routing device and method for routing transactions in an integrated circuit.
  34. Jensen, Michael Gottlieb, Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch.
  35. Jensen, Michael Gottlieb, Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch.
  36. Jensen, Michael Gottlieb, Transaction selector employing transaction queue group priorities in multi-port switch.
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