Method and apparatus for reducing fixed charge in semiconductor device layers
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/58
출원번호
US-0228697
(2002-08-26)
발명자
/ 주소
Iyer, Ravi
Thakur, Randhir P. S.
Rhodes, Howard E.
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보
피인용 횟수 :
0인용 특허 :
23
초록▼
The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resu
The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.
대표청구항▼
The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resu
The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices. The field effect transistor described in claim 1 wherein the dielectric material is silicon oxide. 3. The field effect transistor described in claim 1 wherein the layer of dielectric material has a thickness between about 4,500 and 5,500 Angstroms. 4. The field effect transistor described in claim 1 wherein the transistor has a cutoff frequency greater than about 7 Ghz. 5. The field effect transistor described in claim 1 wherein the transistor, has a thermal dissipation capability such that when operating at a power level between about 15 and 60 watts, a maximum inner temperature of between about 40 and 50° C. is reached. 6. A field effect transistor, comprising: a body of P- silicon having an upper surface and left and right edges; immediately below the P- silicon, a layer of P+ silicon as a source contact; a sinker of P+ silicon extending away from the left edge by an amount and extending downwards from the upper surface into the P+ layer; a first layer of N+ silicon, having a first thickness, between about 2,500 and 3,500 Angstroms, adjacent to, and extending away from, the sinker for a first width as a source region; a second layer of N+ silicon, having a thickness between about 6,500 and 8,500 Angstroms, extending away from the right edge for a second width as an outer drain region; a layer of N- silicon, having a second thickness, adjacent to, and extending away from, said outer drain region towards the first N+ layer as a lightly doped inner drain region; a gap between the source region and the inner drain region as a channel region; over said channel region a layer of gate oxide overcoated with a gate electrode; a layer of a conductive material,on said upper surface that contacts both the P+ sinker and the source region; a drain electrode over the outer drain region; and a layer of dielectric material immediately below the entire outer drain region and below part of the inner drain region, said dielectric layer serving to reduce parasitic capacitance between the drain region and the source region, thereby improving high frequency performance of the transistor. 7. The field effect transistor described in claim 6 wherein said first thickness is between about 2,500 and 3,500 Angstroms for the source and between about 6,500 and 8,500 Angstroms for the drain. 8. The field effect transistor described in claim 6 wherein said first width is between about 50 and 90 microns. 9. The field effect transistor described in claim 6 wherein said second thickness is between about 1,500 and 3,500 Angstroms. 10. The field effect transistor described in claim 6 wherein said second width is between about 50 and 90 microns. 11. The field effect transistor described in claim 6 wherein the gap has a width between about 50 and 90 microns. 12. The field effect transistor described in claim 6 wherein the layer of dielectric material contacts an entire lower portion of the outer drain region.
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이 특허에 인용된 특허 (23)
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