IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0870519
(2001-06-01)
|
우선권정보 |
KR-0030113 (2000-06-01) |
발명자
/ 주소 |
- Bae, Mun Sik
- Jeong, Seog Yeong
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
24 인용 특허 :
7 |
초록
▼
A touch switching apparatus includes: a switching unit for evenly illuminating on a touch unit manipulated by a user among touch units with marks; and a driving circuit for driving the switching unit when detecting the manipulation. The touch switching apparatus includes: an insulating unit for indu
A touch switching apparatus includes: a switching unit for evenly illuminating on a touch unit manipulated by a user among touch units with marks; and a driving circuit for driving the switching unit when detecting the manipulation. The touch switching apparatus includes: an insulating unit for inducing a capacitance as a user's body contacts and presented with a touch switch for manipulation of an instrument; a conductive unit for detecting a capacitance through the medium (dielectric) of a user's body contacting the insulating unit; a flat light emitting device for providing a backlight to the insulating unit to visibly express a corresponding switching unit when a body contact is detected by the conductive unit; and a drive unit for detecting whether a switch has been manipulated according to a change in a capacitance made by the conductive unit.
대표청구항
▼
A touch switching apparatus includes: a switching unit for evenly illuminating on a touch unit manipulated by a user among touch units with marks; and a driving circuit for driving the switching unit when detecting the manipulation. The touch switching apparatus includes: an insulating unit for indu
A touch switching apparatus includes: a switching unit for evenly illuminating on a touch unit manipulated by a user among touch units with marks; and a driving circuit for driving the switching unit when detecting the manipulation. The touch switching apparatus includes: an insulating unit for inducing a capacitance as a user's body contacts and presented with a touch switch for manipulation of an instrument; a conductive unit for detecting a capacitance through the medium (dielectric) of a user's body contacting the insulating unit; a flat light emitting device for providing a backlight to the insulating unit to visibly express a corresponding switching unit when a body contact is detected by the conductive unit; and a drive unit for detecting whether a switch has been manipulated according to a change in a capacitance made by the conductive unit. he substrate of claim 1, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the first die side surface of the substrate. 8. The substrate of claim 1, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the first die side surface of the substrate and a portion thereof located in the substrate. 9. The substrate of claim 1, where the substrate comprises a printed circuit board. 10. The substrate of claim 1, wherein a multilayer substrate includes a plurality of bond pads connected to the plurality of circuit traces. 11. The substrate of claim 10, wherein the plurality of bond pads is located on the second attachment surface of the substrate. 12. The substrate of claim 10, further including a plurality of bond pads located on the first die side surface of the substrate. 13. A substrate having a plurality of circuits for connecting one or more bare semiconductor dice to another substrate, each bare semiconductor die of the one or more bare semiconductor dice having a plurality of bond pads on a portion of a surface thereof for connecting to said the another substrate, the substrate using a plurality of bond wires for connecting between the plurality of bond pads on each bare semiconductor die of the one or more bare semiconductor dice and the plurality of circuits on the substrate, comprising: a multilayer substrate having a first die side surface for attaching thereto a portion of the surfaces having the plurality of bond pads thereon of the one or more bare semiconductor dice, a second attachment surface having a plurality of bond pads located thereon for connecting the plurality of bond wires thereto, one or more vias extending therethrough for the plurality of bond wires to extend therethrough from the plurality of bond pads of the one or more bare semiconductor dice, and a plurality of circuit traces having at least one circuit trace connected to at least one bond pad of the plurality of bond pads of the second attachment surface for connecting the plurality of bond wires connected to the plurality of bond pads of the one or more bare semiconductor dice and for electrically connecting between the one or more bare semiconductor dice and the another substrate, at least a portion of at least one circuit trace of the plurality of circuit traces substantially extending through at least one layer of the multilayer substrate; and a plurality of electrical connectors located on the second attachment surface of the multilayer substrate for electrically connecting the multilayer substrate to the another substrate, the plurality of electrical connectors connected to the plurality of circuit traces. 14. The substrate of claim 13, wherein the plurality of electrical connectors comprises a plurality of solder balls. 15. The substrate of claim 13, wherein the plurality of electrical connectors comprises a plurality of pins. 16. The substrate of claim 13, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located in the multilayer substrate. 17. The substrate of claim 13, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the second attachment surface of the multilayer substrate. 18. The substrate of claim 13, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the second attachment surface of the multilayer substrate and a portion thereof located in the multilayer substrate. 19. The substrate of claim 13, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereo f having a portion thereof located on the first die side surface of the multilayer substrate. 20. The substrate of claim 13, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the first die side surface of the multilayer substrate and a portion thereof located in the multilayer substrate. 21. The substrate of claim 13, wherein the multilayer substrate comprises a printed circuit board. 22. The substrate of claim 13, wherein the multilayer substrate further includes a plurality of bond pads connected to the plurality of circuit traces. 23. A substrate having a plurality of circuits thereon for connecting a plurality of bare semiconductor dice to another substrate, each bare semiconductor die of the plurality of bare semiconductor dice having a plurality of bond pads on a portion of a surface thereof for connecting to the another substrate, the substrate using a plurality of bond wires for connecting between the plurality of bond pads on the plurality of bare semiconductor dice and a plurality of circuits on the substrate, comprising: a substrate having at least one layer, having a first die side surface for attaching thereto a portion of the surfaces having the plurality of bond pads thereon of the plurality of bare semiconductor dice, a second attachment surface having a plurality of bond pads located thereon for connecting the plurality of bond wires thereto, a plurality of vias extending therethrough for the plurality of bond wires to extend therethrough from the plurality of bond pads of the plurality of bare semiconductor dice, and a plurality of circuit traces having at least one circuit trace connected to at least one bond pad of the plurality of bond pads of the second attachment surface for connection to the plurality of bond wires connected to the plurality of bond pads of the plurality of bare semiconductor dice and for electrically connecting between the plurality of bare semiconductor dice and the another substrate, at least a portion of at least one circuit of the plurality of circuits substantially extending through the at least one layer; and a plurality of electrical connectors located on the second attachment surface of the substrate for electrically connecting the substrate and-said-to the another substrate, the plurality of electrical connectors for connecting to the plurality of circuit traces. 24. The substrate of claim 23, wherein the plurality of electrical connectors comprises a plurality of solder balls. 25. The substrate of claim 23, wherein the plurality of electrical connectors comprises a plurality of pins. 26. The substrate of claim 23, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located in the substrate. 27. The substrate of claim 23, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the second attachment surface of the substrate. 28. The substrate of claim 23, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the second attachment surface of the substrate and a portion thereof located in the substrate. 29. The substrate of claim 23, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the first die side surface of the substrate. 30. The substrate of claim 23, wherein the plurality of circuit traces comprises a plurality of circuit traces having at least one circuit trace thereof having a portion thereof located on the first die side surface of the substrate and a portion thereof located in the substrate. 31. The substrate of claim 23, wherein the substrate comprises a
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