초록 ▼

Disclosed is a method for conserving power in a battery-powered electronic appliance having a communications interface including receive mode circuitry and a battery that supplies power to the receive mode circuitry when the receive mode circuitry is enabled. Upon power up of the appliance, the comm

Disclosed is a method for conserving power in a battery-powered electronic appliance having a communications interface including receive mode circuitry and a battery that supplies power to the receive mode circuitry when the receive mode circuitry is enabled. Upon power up of the appliance, the communications interface is initialized, and the receive mode circuitry is enabled to operate in a receive mode. A predetermined enable time is then timed. When the predetermined enable time expires, the receive mode circuitry is disabled.

대표청구항 ▼

Disclosed is a method for conserving power in a battery-powered electronic appliance having a communications interface including receive mode circuitry and a battery that supplies power to the receive mode circuitry when the receive mode circuitry is enabled. Upon power up of the appliance, the comm

Disclosed is a method for conserving power in a battery-powered electronic appliance having a communications interface including receive mode circuitry and a battery that supplies power to the receive mode circuitry when the receive mode circuitry is enabled. Upon power up of the appliance, the communications interface is initialized, and the receive mode circuitry is enabled to operate in a receive mode. A predetermined enable time is then timed. When the predetermined enable time expires, the receive mode circuitry is disabled. at least one processor coupled to receive a first system clock operating at said first clock rate and a second system clock operating at said second clock rate, wherein said at least one processor is configured to operate according to said second system clock, wherein said ratio is an integer number greater than or equal to one, wherein said at least one processor is further coupled to said logic with a serial line over which to receive said initialization information; wherein said logic is configured transmit said initialization information over said serial line to said at least one processor, wherein said logic is further configured to transmit a first state over said serial line prior to said start bit, wherein said start bit includes a second state different from said first state; and wherein said at least one processor is further configured to receive said start bit and to use a transition between said first state and said second state to receive said ratio bit, and wherein said processor is further configured to decode said ratio bit to determine said first clock rate to receive a remainder of said initialization information. 7. The system of claim 6, wherein said at least one processor is further configured to operate at a fast clock rate, wherein the ratio between said fast clock rate and said second clock rate is an integer greater than or equal to one. 8. The computer system of claim 6 further comprising a bridge that includes said memory and said logic. 9. The computer system as recited in claim 6, wherein said at least one processor is further configured to store said one or more ratio bits within a register. 10. The computer system as recited in claim 6, wherein said at least one processor is further configured to receive said one or more ratio bits on an edge of said second clock.