IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
|
출원번호 |
US-0459756
(1999-12-10)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
93 인용 특허 :
175 |
초록
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A reinforced hydroform member having an outer structural member reinforced by a structural foam supported by the outer structural member. The structural foam extends along at least a portion of the length of the outer structural member. The structural foam is a heat-activated epoxy-based resin. As t
A reinforced hydroform member having an outer structural member reinforced by a structural foam supported by the outer structural member. The structural foam extends along at least a portion of the length of the outer structural member. The structural foam is a heat-activated epoxy-based resin. As the foam is heated, it expands and adheres to adjacent surfaces. The preferred structural foam material is commercially available from L&L Products of Romeo, Michigan under the designation L5206, L5207, L5208, or L5209.
대표청구항
▼
A reinforced hydroform member having an outer structural member reinforced by a structural foam supported by the outer structural member. The structural foam extends along at least a portion of the length of the outer structural member. The structural foam is a heat-activated epoxy-based resin. As t
A reinforced hydroform member having an outer structural member reinforced by a structural foam supported by the outer structural member. The structural foam extends along at least a portion of the length of the outer structural member. The structural foam is a heat-activated epoxy-based resin. As the foam is heated, it expands and adheres to adjacent surfaces. The preferred structural foam material is commercially available from L&L Products of Romeo, Michigan under the designation L5206, L5207, L5208, or L5209. rage medium having stored thereon further instructions that, when executed by the computing device, result in attaching a vitality to the load instruction in an instruction cache. 15. A load apparatus, comprising: a computer including a processor and a memory, the processor including at least two caches with different latencies; a load instruction, the load instruction including a data address storing data; a vitality determiner designed to determine a vitality for the load instruction, the vitality determiner including a register file designed to count cycles between the load instruction and a dependent instruction accessing the data and a cache assigner designed to assign the load instruction to one of the caches, based on the vitality and whether the load instruction is non-vital. 16. An apparatus according to claim 15, further comprising an instruction cache designed to store the load instruction and the vitality while the load instruction is pending. 17. An apparatus according to claim 15, further comprising a load analyzer designed to determine whether the load instruction is vital or non-vital. 18. A method for performing load instructions, the method comprising: identifying a load instruction, the load instruction including a data address storing data; classifying the load instruction as vital if the data is demanded immediately by a dependent instruction; selecting, from at least a first cache including a minimum latency and a second cache including a higher latency, the second cache for the load instruction if the load instruction is non-vital; selecting; the first cache for the load instruction if the load instruction is vital; and loading the data from the selected cache. 19. A method according to claim 18, wherein classifying the load instruction includes determining a vitality to the load instruction. 20. A method according to claim 18, wherein selecting includes selecting a cache with a latency no higher than the vitality. 21. A method for performing load instructions, the method comprising: identifying a load instruction, the load instruction including a data address storing data; classifying the load instruction as vital if a dependent branch instruction is predicted wrongly based on the data; selecting one of at least a first cache including a minimum latency and a second cache including a higher latency for the load instruction, so that the selected cache includes a latency higher than the minimum latency if the load instruction is non-vital; and loading the data from the selected cache. 22. A method according to claim 21, wherein selecting includes selecting the first cache if the load instruction is vital. 23. A method according to claim 21, wherein classifying the load instruction includes determining a vitality to the load instruction. 24. A method according to claim 23, wherein selecting includes selecting a cache with a latency no higher than the vitality. 25. A method according to claim 23, wherein determining a vitality includes: counting a number of cycles between the load instruction and an operation accessing the data; and assigning the number of cycles as the vitality to the load instruction. 26. A method according to claim 21, wherein classifying the load instruction includes classifying the load instruction as non-vital if the load instruction is not a vital load instruction. 27. A method according to claim 21, further comprising attaching a vitality to the load instruction in an instruction cache. 28. An article comprising: a storage medium, said storage medium having stored thereon instructions that, when executed by a computing device, result in: identifying a load instruction, the load instruction including a data address storing data; classifying the load instruction as vital if a dependent branch instruction is predicted wrongly based on the data; selecting one of at least a first cache including a minimum latency and a second cache including a higher latency for the load instruction, so that the selected cache includes a latency higher than the minimum latency if the load instruction is non-vital; and loading the data from the selected cache. 29. An article according to claim 28, wherein selecting includes selecting the first cache if the load instruction is vital. 30. An article according to claim 28, wherein classifying the load instruction includes determining a vitality to the load instruction. 31. A method according to claim 30, wherein selecting includes selecting a cache with a latency no higher than the vitality. 32. A method according to claim 30, wherein determining a vitality includes: counting a number of cycles between the load instruction and an operation accessing the data; and assigning the number of cycles as the vitality to the load instruction. 33. An article according to claim 28, wherein classifying the load instruction includes classifying the load instruction as non-vital if the load instruction is not a vital load instruction. 34. An article according to claim 28, the storage medium having stored thereon further instructions that, when executed by the computing device, result in attaching a vitality to the load instruction in an instruction cache. 35. A method for performing load instructions, the method comprising: identifying a load instruction, the load instruction including a data address storing data; classifying the load instruction as vital if a dependent branch instruction is predicted wrongly based on the data; selecting, from at least a first cache including a minimum latency and a second cache including a higher latency, the second cache for the load instruction if the load instruction is non-vital; selecting the first cache for the load instruction if the load instruction is vital; and loading the data from the selected cache. 36. A method according to claim 35, wherein classifying the load instruction includes determining a vitality to the load instruction. 37. A method according to claim 36, wherein selecting includes selecting a cache with a latency no higher than the vitality.
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