초록 ▼

A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an ext

A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover or enclosure disposed around at least a portion of the substrate and the conductive link. The package can be filled with a liquid or a pressurized gas to transfer heat away from the conductive link. In one embodiment, the enclosure can have a composition substantially identical to the composition of the conductive links and the enclosure can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.

대표청구항 ▼

A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an ext

A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover or enclosure disposed around at least a portion of the substrate and the conductive link. The package can be filled with a liquid or a pressurized gas to transfer heat away from the conductive link. In one embodiment, the enclosure can have a composition substantially identical to the composition of the conductive links and the enclosure can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points. nsulator (SOI) transistor source connections for SOI transistor devices as recited in claim 1 wherein said SOI transistor is a P-channel field effect transistor, and said second predefined buried conduction layer in the SOI semiconductor structure comprising P type bulk silicon material. 6. A SOI semiconductor structure for implementing silicon-on-insulator (SOI) transistor source connections for SOI transistor devices as recited in claim 1 wherein said second predefined buried conduction layer in the SOI semiconductor structure defines a ground or a power source. 7. A SOI semiconductor structure for implementing silicon-on-insulator (SOI) transistor source connections for SOI transistor devices as recited in claim 1 wherein said conductor is formed of tungsten. 8. A SOI semiconductor structure for implementing silicon-on-insulator (SOI) transistor source connections for SOI transistor devices as recited in claim 1 wherein said conductor is formed of an electrically conductive material selected from the group including copper, conductive doped silicon, platinum, palladium, rhodium, aluminum, tantalum, titanium, tungsten and titanium-tungsten.