IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0998369
(2001-11-30)
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발명자
/ 주소 |
- Bennett, Robert J.
- Gonzalez, Jr., Gustavo A.
- Cwirzen, Casimir Z.
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출원인 / 주소 |
- Corning Cable Systems LLC
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
5 인용 특허 :
15 |
초록
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A surge protector having a failsafe mechanism including at least one overvoltage protection element, at least one arm assembly, at least one ground element, at least one resilient member, and at least one protrusion. The at least one resilient member is electrically connected to the at least one gro
A surge protector having a failsafe mechanism including at least one overvoltage protection element, at least one arm assembly, at least one ground element, at least one resilient member, and at least one protrusion. The at least one resilient member is electrically connected to the at least one ground element and the at least one protrusion is generally positioned between the at least one resilient member and the at least one arm assembly. The at least one protrusion is in thermal contact with the at least one resilient member, prevents the at least one resilient member from electrically contacting the at least one arm assembly during normal operation, and is spaced away from the at least one arm assembly. As a result of a sustained overvoltage condition, the temperature of the at least one resilient member increases thereby softening the at least one protrusion and allowing the at least one resilient member to electrically contact the at least one arm assembly to short the at least one arm assembly to the ground element.
대표청구항
▼
A surge protector having a failsafe mechanism including at least one overvoltage protection element, at least one arm assembly, at least one ground element, at least one resilient member, and at least one protrusion. The at least one resilient member is electrically connected to the at least one gro
A surge protector having a failsafe mechanism including at least one overvoltage protection element, at least one arm assembly, at least one ground element, at least one resilient member, and at least one protrusion. The at least one resilient member is electrically connected to the at least one ground element and the at least one protrusion is generally positioned between the at least one resilient member and the at least one arm assembly. The at least one protrusion is in thermal contact with the at least one resilient member, prevents the at least one resilient member from electrically contacting the at least one arm assembly during normal operation, and is spaced away from the at least one arm assembly. As a result of a sustained overvoltage condition, the temperature of the at least one resilient member increases thereby softening the at least one protrusion and allowing the at least one resilient member to electrically contact the at least one arm assembly to short the at least one arm assembly to the ground element. ross the first power supply line VDD1 and the second power supply line VDD2 having an ESDD output, a single CMOS Controlled Lateral SCR (CLSCR) device having a gate electrode and a P+ region and an N+ region with the gate electrode connected to the ESDD output, a diode string comprising a plurality of diodes each having an anode and a cathode connected in series with a proximal diode and a distal diode, the P+ region of the single CLSCR connected to the first power supply line VDD1, the N+ region of the single CLSCR connected to the proximal diode, and the distal diode connected to a second power supply line VDD2, and a plurality of series connected diodes each having an anode and a cathode between the first power supply line and the second power supply line with the reverse polarity with respect to the diode string. 6. The device of claim 5 wherein the ESDD circuit includes a resistor and a capacitor having a junction therebetween connected in series between the first power supply line and the second power supply line with the ESDD output line connected to the junction between the resistor and the capacitor. 7. The device of claim 5 wherein: the CMOS Controlled Lateral SCR device comprises a PMOS Controlled Lateral SCR (PCLSCR), and the ESDD circuit includes a resistor and a capacitor having a junction therebetween connected in series between the first power supply line and the second power supply line with the ESDD output line connected to the junction between the resistor and the capacitor. 8. The device of claim 5 wherein: the CMOS Controlled Lateral SCR device comprises a NMOS Controlled Lateral SCR (NCLSCR), and the ESDD circuit includes a resistor and a capacitor having a junction therebetween connected in series between the first power supply line and the second power supply line with the ESDD output line connected to the junction between the resistor and the capacitor. 9. An ESD protection circuit for an integrated circuit device comprising: a first power supply line VDD1 and a second power supply line VDD2 where voltage on the first power supply line is greater than voltage on the second power supply line, a single NMOS Controlled Lateral SCR (CLSCR) device having a gate electrode and a P+ region and an N+ region, a diode string comprising a plurality of diodes each having an anode and a cathode connected in series with a proximal diode and a distal diode, the P+ region of the single CLSCR connected to the first power supply line VDD1, the N+ region of the single CLSCR connected to the proximal diode, and the distal diode connected to the second power supply line VDD2, with the gate electrode connected to the anode of the proximal diode, a plurality of series connected diodes each having an anode and a cathode between the first power supply line and the second power supply line with the reverse polarity with respect to the diode string. 10. An ESD protection circuit for an integrated circuit device comprising: a first power supply line VSS1 and a second power supply line VSS2, an electrostatic discharge detection (ESDD) circuit connected across the power supply line VSS1 and the second power supply line VSS2 having an ESDD output, a single PMOS Controlled Lateral SCR (PCLSCR) device having a gate electrode and a P+ region and an N+ region with the gate electrode connected to the ESDD output, a diode string comprising a plurality of diodes each having an anode and a cathode connected in series with a proximal diode and a distal diode, the P+ region of the single PCLSCR connected to the first power supply line VSS 1, the N+ region of the single PCLSCR connected to the proximal diode, and the distal diode connected to the second power supply line VSS2, and a plurality of series connected diodes each having an anode and a cathode between the first power supply line and the second power supply line with the reverse polarity with respect to the diode string. 11. The device of c laim 10 wherein the ESDD circuit includes a resistor and a capacitor having a junction therebetween connected in series between the first power supply line and the second power supply line with the ESDD output line connected to the junction between the resistor and the capacitor. 12. The device of claim 10 wherein the ESDD circuit includes a resistor and a capacitor having a junction therebetween connected in series between the first power supply line and the second power supply line with the ESDD output line connected to the junction between the resistor and the capacitor, and the resistor connected to VSS1 and the capacitor connected to VSS2. 13. An ESD protection circuit for an integrated circuit device consisting of: a power supply line and a ground line, an electrostatic discharge detection (ESDD) circuit connected across the power supply line VDD and the ground line VSS having an ESDD output line, a single NMOS Controlled Lateral SCR (NCLSCR) device having a gate electrode and a P+ region and an N+ region with the gate electrode connected to the ESDD output line, a diode string comprising a plurality of diodes each having an anode and a cathode connected in series with a proximal diode and a distal diode, the P+ region of the single NCLSCR connected to the power supply line VDD, the N+ region of the single NCLSCR connected to the proximal diode, and the distal diode connected to the ground line VSS. 14. An ESD-protection circuit for an integrated circuit device consisting of: a power supply line and a ground line, an electrostatic discharge detection (ESDD) circuit connected across the power supply line VDD and the ground line VSS having an ESDD output line, a single PMOS Controlled Lateral SCR (PCLSCR) device having a gate electrode and a P+ region and an N+ region with the gate electrode connected to the ESDD output line, a diode string comprising a plurality of diodes each having an anode and a cathode connected in series with a proximal diode and a distal diode, the P+ region of the single PCLSCR connected to the power supply line VDD, the N+ region of the single PCLSCR connected to the proximal diode, and the distal diode connected to the ground line VSS. 15. An ESD protection circuit for an integrated circuit device consisting of: an I/O signal line and a ground line, an electrostatic discharge detection (ESDD) circuit connected across the I/O signal line and the ground line, the I/O signal line and the ground line having an ESDD output line, a single NMOS Controlled Lateral SCR (NCLSCR) having a gate, a P+ region and an N+ region with the gate connected to the ESDD output line, a diode string comprising a plurality of diodes each having an anode and a cathode connected in series with a proximal diode and a distal diode, the P+ region of the single NCLSCR connected to the I/O signal line, the N+ region of the single NCLSCR connected to the proximal diode, and the distal diode connected to the ground line. 16. An ESD protection circuit for an integrated circuit device consisting of: an I/O signal line and a ground line, an electrostatic discharge detection (ESDD) circuit connected across the I/O signal line and the ground line, the I/O signal line and the ground line having an ESDD output line, a single PMOS Controlled Lateral SCR (PCLSCR) having a gate, a P+ region and an N+ region with the gate connected to the ESDD output line, a diode string comprising a plurality of diodes each having an anode and a cathode connected in series with a proximal diode and a distal diode, the P+ region of the single PCLSCR connected to the I/O signal line, the N+ region of the single PCLSCR connected to the proximal diode, and the distal diode connected to the ground line.
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