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Pulsed-mode RF bias for side-wall coverage improvement 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/31
출원번호 US-0037018 (2001-11-07)
발명자 / 주소
  • Forster, John
  • Gopalraja, Praburam
  • Stimson, Bradley O.
  • Hong, Liubo
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Moser, Patterson & Sheridan
인용정보 피인용 횟수 : 16  인용 특허 : 46

초록

The present invention provides a method and apparatus for achieving conformal step coverage of one or more materials on a substrate using sputtered ionized material. A target provides a source of material to be sputtered by a plasma and then ionized by an inductive coil, thereby producing electrons

대표청구항

The present invention provides a method and apparatus for achieving conformal step coverage of one or more materials on a substrate using sputtered ionized material. A target provides a source of material to be sputtered by a plasma and then ionized by an inductive coil, thereby producing electrons

이 특허에 인용된 특허 (46)

  1. Mintz Donald M. (Sunnyvale CA), Apparatus for manufacturing planarized aluminum films.
  2. Sellers Jeff C. (Palmyra NY), Arc control and switching element protection for pulsed dc cathode sputtering power supply.
  3. Xu Zheng ; Kieu Hoa, Deposition process for coating or filling re-entry shaped contact holes.
  4. Shrinkle Louis J. (Leucadia CA), Disk drive with PRML read channel calibration using a noise generator.
  5. Drummond Geoffrey N. ; Scholl Richard A., Enhanced reactive DC sputtering system.
  6. Sellers Jeff C., Etch process employing asymmetric bipolar pulsed DC.
  7. Teong Su-Ping (Singapore SGX), Etch stop for copper damascene process.
  8. Joshi Rajiv Vasant ; Tejwani Manu Jamnadas ; Srikrishnan Kris Venkatraman, High aspect ratio low resistivity lines/vias with a tungsten-germanium alloy hard cap.
  9. Givens John H. ; Leiphart Shane B., In situ preclean in a PVD chamber with a biased substrate configuration.
  10. Grosman Jerry (2616 S. Burke Pasadena TX 77502) Haden ; Jr. Wm. H. (717 Crenshaw Rd. Pasadena TX 77504), Ion plating method and apparatus.
  11. Kobayashi Masahiko,JPX ; Takahashi Nobuyuki,JPX, Ionizing sputter device using a coil shield.
  12. Hu Yongjun, Low angle, low energy physical vapor deposition of alloys.
  13. Mark Gunter (Ottersweier DEX), Low frequency, pulsed, bipolar power supply for a plasma chamber.
  14. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  15. Grabarz Henry J. (Huntington CT) Grill Alfred (White Plains NY) Holber William M. (New York NY) Logan Joseph S. (Poughkeepsie NY) Yeh James T. C. (Katonah NY), Method and apparatus for filing high aspect patterns with metal.
  16. Goolsby Peter G. (Phoenix AZ) Ramirez Dan R. (Chandler AZ) Lai Lei P. (Glendale AZ), Method and apparatus for plating metals.
  17. Okamura Nobuyuki (Kawasaki JPX) Yamagami Atsushi (Kawasaki JPX), Method for forming a functional deposited film by bias sputtering process at a relatively low substrate temperature.
  18. Nihei Masayasu (Hitachi JPX) Onuki Jin (Hitachi JPX) Koubuchi Yasushi (Hitachi JPX) Miyazaki Kunio (Hitachi JPX) Itagaki Tatsuo (Tokyo JPX), Method of and apparatus for sputtering.
  19. Pan Ju-Don T. (Austin TX), Method of deposition of metal into cavities on a substrate.
  20. Reid Jonathan D. ; Contolini Robert J. ; Opocensky Edward C. ; Patton Evan E. ; Broadbent Eliot K., Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer.
  21. Yamamoto Hiroshi (Chiba JPX) Takeyasu Nobuyuki (Chiba JPX) Ohta Tomohiro (Urayasu JPX), Method of forming multilayered wiring structure in semiconductor device.
  22. Chan Lap ; Zheng Jia Zhen,SGX, Method of manufacturing copper interconnect with top barrier layer.
  23. Inohara Masahiro,JPX ; Anand Minakshisundaran Balasubramanian,JPX ; Matsuno Tadashi,JPX, Method of manufacturing semiconductor device having multi-layer wiring structure with diffusion preventing film.
  24. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  25. Simon Andrew H. ; Uzoh Cyprian E., Open-bottomed via liner structure and method for fabricating same.
  26. Jokinen Olli J. (Kirkkonummi FIX) Petander Lars (Vaasa FIX) Virta Pirkko J. (Muhos FIX), Paper-making method and a combination of ingredients to be used in it.
  27. Lou Chine-Gie,TWX, Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits.
  28. Tomioka Kazuhiro,JPX, Plasma processing apparatus and method.
  29. Nieh Simon K. (Monrovia CA) Matossian Jesse N. (Canoga Park CA) Krajenbrink Frans G. (Newbury Park CA), Plasma-enhanced magnetron-sputtered deposition of materials.
  30. Sellers Jeff C., Preferential sputtering of insulators from conductive targets.
  31. Sellers Jeff C. (Palmyra NY), Preferential sputtering of insulators from conductive targets.
  32. Hubel Egon,DEX, Process and circuitry for generating current pulses for electrolytic metal deposition.
  33. Fu Jianming ; Chen Fusen, Process for forming improved titanium-containing barrier layers.
  34. Agarwala Birendra N. (Hopewell Junction NY), Process of making pad structure for solder ball limiting metallurgy having reduced edge stress.
  35. Martin James L. ; Menard Stephane ; Michelen David N., Programmed pulse electroplating process.
  36. Dubin Valery ; Ting Chiu ; Cheung Robin W., Pulse electroplating copper or copper alloys.
  37. John Forster ; Praburam Gopalraja ; Bradley O. Stimson ; Liubo Hong, Pulsed-mode RF bias for sidewall coverage improvement.
  38. Cote William J. (Poughquag NY) Lee Pei-Ing P. (Williston VT) Sandwick Thomas E. (Hopewell Junction NY) Vollmer Bernd M. (Wappingers Falls NY) Vynorius Victor (Pleasant Valley NY) Wolff Stuart H. (Tul, Refractory metal capped low resistivity metal conductor lines and vias.
  39. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  40. Mosely Roderick Craig ; Chen Liang-Yuh ; Guo Ted, Semi-selective chemical vapor deposition.
  41. Ohmi Tadahiro (1-17-301 ; Komegabukuro 2-chome Sendai-shi ; Miyagi-Ken 980 JPX), Semiconductor manufacturing apparatus.
  42. Hurwitt Steven D. (Park Ridge NJ) Wagner Israel (Monsey NY) Hieronymi Robert (Rock Cavern NY) Van Nutt Charles (Monroe NY) Edwards Richard C. (Ringwood NJ) Messina Donald A. (Valley Cottage NY), Sputter coating process control method and apparatus.
  43. Shimamura Hideaki (Yokohama JPX) Sakata Masao (Yokohama JPX) Kobayashi Shigeru (Tokyo JPX) Yoneoka Yuji (Yokohama JPX) Kamei Tsuneaki (Kanagawa JPX) Kawahito Tsuneyoshi (Yokohama JPX) Fujita Shoyo (G, Sputtering process and an apparatus for carrying out the same.
  44. Tanaka Yoichiro, Step coverage and overhang improvement by pedestal bias voltage modulation.
  45. Xu Zheng (Foster City CA), Synchronous modulation bias sputter method and apparatus for complete planarization of metal films.
  46. Yao Tse-Yong ; Xu Zheng ; Ngan Kenny King-tai ; Chen Xing ; Urbahn John ; Bourget Lawrence P., Use of pulsed-DC wafer bias for filling vias/trenches with metal in HDP physical vapor deposition.

이 특허를 인용한 특허 (16)

  1. Metzner, Craig R.; Kher, Shreyas S.; Gopal, Vidyut; Han, Shixue; Athreya, Shankarram A., ALD metal oxide deposition process using direct oxidation.
  2. Metzner, Craig R.; Kher, Shreyas S.; Gopal, Vidyut; Han, Shixue; Athreya, Shankarram A., ALD metal oxide deposition process using direct oxidation.
  3. Chistyakov, Roman; Abraham, Bassam Hanna, Apparatus and method for sputtering hard coatings.
  4. Lee, Eal; Truong, Nicole; Prater, Robert; Sand, Norm, Coils utilized in vapor deposition applications and methods of production.
  5. Stern,Lewis; Albright,John, Deposition of tensile and compressive stressed materials.
  6. Winterhalter, Markus; Mann, Ekkehard, Driving at least two high frequency-power generators.
  7. Narwankar, Pravin K.; Higashi, Gregg, Formation of a silicon oxynitride layer on a high-k dielectric material.
  8. Chua, Thai Cheng; Hung, Steven; Liu, Patricia M.; Sato, Tatsuya; Paterson, Alex M.; Todorov, Valentin; Holland, John P., Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system.
  9. Olsen, Christopher Sean; Chua, Thai Cheng; Hung, Steven; Liu, Patricia M.; Sato, Tatsuya; Paterson, Alex M.; Todorow, Valentin; Holland, John P., Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system.
  10. Nagarkatti, Siddarth; Tian, Feng; Lam, David; Rashid, Abdul; Benzerrouk, Souheil; Bystryak, Ilya; Menzer, David; Schuss, Jack J.; Ambrosina, Jesse E., Method and system for controlling radio frequency power.
  11. Nagarkatti, Siddharth; Tian, Feng; Lam, David; Rashid, Abdul; Benzerrouk, Souheil; Bystryak, Ilya; Menzer, David; Schuss, Jack J.; Ambrosina, Jesse E., Method and system for controlling radio frequency power.
  12. Chua, Thai Cheng; Paterson, Alex M.; Hung, Steven; Liu, Patricia M.; Sato, Tatsuya; Todorow, Valentin; Holland, John P., Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus.
  13. Chistyakov, Roman; Abraham, Bassam Hanna, Method of ionized physical vapor desposition sputter coating high aspect-ratio structures.
  14. Chistyakov, Roman, Methods and apparatus for generating strongly-ionized plasmas with ionizational instabilities.
  15. Rajagopalan, Nagarajan; Han, Xinhai; Yamase, Ryan; Park, Ji Ae; Patel, Shamik; Nowak, Thomas; Cui, Zhengjiang “David”; Naik, Mehul; Park, Heung Lak; Ding, Ran; Kim, Bok Hoen, Silicon nitride passivation layer for covering high aspect ratio features.
  16. Blattner, Manfred; Winterhalter, Markus; Mann, Ekkehard, Supplying RF power to a plasma process.
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