IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0087361
(2002-03-01)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Kubida, William J.Meza, Peter J.Hogan & Hartson LLP
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인용정보 |
피인용 횟수 :
15 인용 특허 :
99 |
초록
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A single transistor ("1T") ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric. The memory cell of the present invention comprises a substrate, an overlying ferroelectric layer, which may comprise a film of rare ea
A single transistor ("1T") ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric. The memory cell of the present invention comprises a substrate, an overlying ferroelectric layer, which may comprise a film of rare earth manganite, and an interfacial oxide layer intermediate the substrate and the ferroelectric layer. In a preferred embodiment, the ferroelectric material utilized in an implementation of the present invention may be deposited by metallorganic chemical vapor deposition ("MOCVD") or other techniques and exhibits a low relative dielectric permittivity of around 10 and forms an interfacial layer with a relative dielectric permittivity larger than that of SiO2,which makes it particularly suitable for a 1T cell.
대표청구항
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1. An integrated circuit device comprising at least one memory cell comprising: a substrate having source and drain regions formed therein; an interfacial layer overlying said substrate substantially intermediate said source and drain regions; a ferroelectric layer overlying said interfacial la
1. An integrated circuit device comprising at least one memory cell comprising: a substrate having source and drain regions formed therein; an interfacial layer overlying said substrate substantially intermediate said source and drain regions; a ferroelectric layer overlying said interfacial layer; a gate electrode overlying said ferroelectric layer; and wherein said interfacial layer substantially comprises silicon, oxygen and at least one of the elements selected from the group comprising A=Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu or Sc having the general formula SixOyAz,where x, y, and z are values between about 0.1 and 10. 2. The integrated circuit device of claim 1 wherein said substrate comprises Si. 3. The integrated circuit device of claim 1 wherein said ferroelectric layer substantially comprises a material having a general formula AxMnyOz,where x,y,z vary from about 0.1 to 10 and A is a rare earth selected from a group comprising Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y or Sc. 4. The integrated circuit device of claim 1 wherein said gate electrode is selected from a group comprising platinum, gold or any other noble metal. 5. The integrated circuit device of claim 1 wherein said gate electrode is selected from a group comprising iridium, rhodium, ruthenium or oxides thereof. 6. The integrated circuit device of claim 1 wherein said gate electrode is selected from a group comprising doped polycrystalline silicon or a metal silicide. 7. An integrated circuit device formed on a single substrate including a memory array having a plurality of memory cells coupled to at least one word line, plate line and bit line of said memory array, at least one of said memory cells comprising: a 1T transistor having a ferroelectric dielectric formed intermediate of said substrate and a control terminal thereof coupled to said word line, said transistor further comprising first and second terminals coupled respectively to said bit line and plate line; an interfacial layer in contact with said ferroelectric dielectric interposed between said ferroelectric dielectric and said substrate; and wherein said interfacial layer is an oxide of a material selected from a group comprising A=Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu or Sc having the general formula AxSiyOz,where x,y are values between about 0.1 and 10. 8. The integrated circuit device of claim 7 wherein said ferroelectric dielectric is selected from a group comprising rare earth, Yttrium or Scandium manganates. 9. The integrated circuit device of claim 7 wherein a ratio of a thickness of said ferroelectric layer to that of said interfacial layer is substantially 3:1 or less.
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