초록 ▼

A system includes a storage medium storing contextual information about a target or target area, and a simulator communicatively coupled to the storage medium and operable to receive the contextual information. The simulator is operable to generate a set of simulated information about the target usi

A system includes a storage medium storing contextual information about a target or target area, and a simulator communicatively coupled to the storage medium and operable to receive the contextual information. The simulator is operable to generate a set of simulated information about the target using the contextual information. The system further includes a sensor operable to collect a set of actual information about the target. A comparator is operable to generate a set of delta information in response to differences between the set of simulated information and the set of actual information. The delta information is transmitted and added to a second set of simulated information to generate a set of information that is substantially similar to the set of actual information.

대표청구항 ▼

A system includes a storage medium storing contextual information about a target or target area, and a simulator communicatively coupled to the storage medium and operable to receive the contextual information. The simulator is operable to generate a set of simulated information about the target usi

A system includes a storage medium storing contextual information about a target or target area, and a simulator communicatively coupled to the storage medium and operable to receive the contextual information. The simulator is operable to generate a set of simulated information about the target using the contextual information. The system further includes a sensor operable to collect a set of actual information about the target. A comparator is operable to generate a set of delta information in response to differences between the set of simulated information and the set of actual information. The delta information is transmitted and added to a second set of simulated information to generate a set of information that is substantially similar to the set of actual information. verter. 2. The sigma delta modulator of claim 1, further comprising a digital filter coupled with the quantizer, the digital filter being adapted to reduce undesirable noise in the quantized output signal. 3. The sigma delta modulator of claim 1, wherein the mismatch amount is greater than or equal to three times the tolerance amount. 4. The sigma delta modulator of claim 3, wherein the tolerance amount is proportional to a standard deviation for the design element value. 5. The sigma delta modulator of claim 3, wherein the tolerance amount is about one standard deviation for the design element value. 6. The sigma delta modulator of claim 1, wherein the tolerance amount is about one standard deviation for the design element value. 7. The sigma delta modulator of claim 1, wherein the filter comprises an integrator. 8. The sigma delta modulator of claim 1, wherein the quantizer comprises a multi-bit analog to digital converter. 9. The sigma delta modulator of claim 1, comprising: a plurality of filters serially coupled between the input signal and the quantizer; and a plurality of digital to analog converters, the individual digital to analog converters being coupled with the quantizer, the dynamic element matching system, and a corresponding one of the plurality of filters; wherein the individual digital to analog converters comprise a plurality of circuit elements, the individual circuit elements having an associated element value, the individual digital to analog converters being adapted to provide an analog feedback signal corresponding to the quantized output signal using circuit elements selected according to the quantized output signal, the plurality of circuit elements of individual digital to analog converters comprising: at least one mismatched circuit element having a mismatched element value differing from a design element value by a mismatch amount, and a plurality of matched circuit elements having element values within a tolerance amount of the design element value, the mismatch amount being greater than the tolerance amount; wherein a first filter receives the input signal and a first analog feedback signal from a first analog to digital converter, the first filter being adapted to provide a first filtered output signal according to the input signal and the analog feedback signal; wherein remaining filters receive a filtered output signal from a preceding filter and an analog feedback signal from a corresponding digital converter and provide a filtered output to a succeeding filter; wherein the quantizer receives a filtered output from a final filter, and provides the quantized output signal corresponding to the input signal; and wherein the dynamic element matching system is coupled with the digital to analog converters and with the quantizer, the dynamic element matching system being adapted to vary the selection of circuit elements of the digital to analog converters. 10. The sigma delta modulator of claim 1, wherein the dynamic element matching system is adapted to vary the selection of circuit elements of the digital to analog converter according to an algorithm, and wherein the algorithm is one of individual level averaging (ILA), group level averaging (GLA), and partial data weighted averaging (partial DWA). 11. The sigma delta modulator of claim 1, wherein the circuit elements are capacitors. 12. The sigma delta modulator of claim 11, wherein the individual circuit elements comprise a capacitor having first and second conductive routing structures for electrically coupling the capacitor with other components in the digital to analog converter, wherein the first and second conductive routing structures of the mismatched circuit element are routed close to one another so as to create a mismatch capacitance in parallel with the capacitor of the mismatched circuit element, the mismatch capacitance having a value of about the mismatch amount or more, and wherein the first and second conductive routing structures of the individual matched circuit elements are spaced from one another so as to provide a match capacitance in parallel with the capacitor of the matched circuit element, the match capacitance having a value of about the tolerance amount or less. 13. The digital to analog converter of claim 11, wherein the tolerance amount is about one standard deviation for the design element value. 14. The sigma delta modulator of claim 1, wherein the mismatched circuit element comprises a first circuit element having an element value within the tolerance amount of the design element value and a second circuit element having a value of about the mismatch amount or more. 15. A digital to analog converter for providing an analog feedback signal corresponding to a quantized output signal in a sigma delta modulator, the digital to analog converter comprising: a plurality of circuit elements, the individual circuit elements having an associated element value, the digital to analog converter being adapted to provide the analog feedback signal using circuit elements selected according to the quantized output signal, the plurality of circuit elements comprising at least one mismatched circuit element having a mismatched element value differing from a design element value by a mismatch amount, and a plurality of matched circuit elements having element values within a tolerance amount of the design element value, the mismatch amount being greater than the tolerance amount. 16. The digital to analog converter of claim 15, wherein the mismatch amount is greater than or equal to three times the tolerance amount. 17. The digital to analog converter of claim 16, wherein the tolerance amount is proportional to a standard deviation for the design element value. 18. The digital to analog converter of claim 16, wherein the tolerance amount is about one standard deviation for the design element value. 19. The digital to analog converter of claim 15, wherein the circuit elements are capacitors. 20. The digital to analog converter of claim 19, wherein the individual circuit elements comprise a capacitor having first and second conductive routing structures for electrically coupling the capacitor with other components in the digital to analog converter, wherein the first and second conductive routing structures of the mismatched circuit element are routed close to one another so as to create a mismatch capacitance in parallel with the capacitor of the mismatched circuit element, the mismatch capacitance having a value of about the mismatch amount or more, wherein the first and second conductive routing structures of the individual matched circuit elements are spaced from one another so as to provide a match capacitance in parallel with the capacitor of the matched circuit element, the match capacitance having a value of about the tolerance amount or less. 21. The digital to analog converter of claim 19, wherein the mismatch amount is greater than or equal to three times the tolerance amount. 22. The digital to analog converter of claim 21, wherein the tolerance amount is proportional to a standard deviation for the design element value. 23. The digital to analog converter of claim 21, wherein the tolerance amount is about one standard deviation for the design element value. 24. The digital to analog converter of claim 14, wherein the mismatched circuit element comprises a first circuit element having an element value within the tolerance amount of the design element value and a second circuit element having a value of about the mismatch amount or more. 25. A method of fabricating a digital to analog converter for providing an analog feedback signal corresponding to a quantized output signal using a group of circuit elements selected according to the quantized output signal in a sigma delta modulator, the method comprising: providing a plurality of matched circuit elements in the group in a semiconductor device, the matched circuit eleme nts having element values within a tolerance amount of a design element value; and providing at least one mismatched circuit element in the group, the at least one mismatched circuit element having a mismatched element value differing from the design element value by a mismatch amount, the mismatch amount being greater than the tolerance amount. 26. The method of claim 25, further comprising coupling the matched circuit elements and the at least one mismatched circuit element with a dynamic element matching system adapted to vary the selection of circuit elements of the group. 27. The method of claim 25: wherein the circuit elements in the group are capacitors; wherein providing the plurality of matched circuit elements comprises: providing a plurality of matched capacitors having capacitance values within the tolerance amount of a design capacitance value; individually providing first and second conductive routing structures for electrically coupling the matched capacitors with other components in the digital to analog converter; and spacing the first and second conductive routing structures of the individual matched capacitors from one another so as to provide a match capacitance in parallel with the matched capacitor, the match capacitance having a value of about the tolerance amount or less; and wherein providing the at least one mismatched circuit element comprises: providing at least one capacitor having a capacitance value within the tolerance amount of the design capacitance value; providing first and second conductive routing structures for electrically coupling the at least one capacitor with other components in the digital to analog converter; and spacing the first and second conductive routing structures of the at least one capacitor from one another so as to provide a mismatch capacitance in parallel with the at least one capacitor, the mismatch capacitance having a value of about the mismatch amount or more. 28. The method of claim 25, wherein the circuit elements in the group are capacitors, wherein the matched circuit elements are capacitors having capacitance values within a tolerance amount of a design capacitance value, and wherein providing the at least one mismatched circuit element comprises: providing a first capacitor having element value within the tolerance amount of the design capacitance value; providing a second capacitor having a value of about the mismatch amount or more; and coupling the first and second capacitors in parallel to form at least one mismatched capacitor.