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A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an assoc

A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.

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A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an assoc

A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol. apparatus of claim 1, wherein the controller implements a least recently used replacement algorithm to evict an entry in the buffer. 8. The apparatus of claim 1, wherein the table includes a plurality of registers to store a plurality of bits making up a prefetch address tag. 9. The apparatus of claim 8, wherein the plurality of registers further store a plurality of Least Recently Used (LRU) values, each indicative of a usage of the corresponding evicted prefetch address. 10. A method comprising: comparing a prefetch address to a list of previously generated prefetch addresses that were evicted from a buffer; and determining whether to prefetch data corresponding to the prefetch address according to the result of the comparison. 11. The method as recited in claim 10, wherein prior to comparing the prefetch address the method further comprises: receiving a memory request from a processor, the memory request including an address of corresponding data located in a memory; and using the memory request to generate the prefetch address according to a prefetching technique. 12. The method of claim 11, further comprising: searching a cache to determine whether a data corresponding to the memory request is contained in a cache and if so then returning the data to the processor. 13. The method of claim 12, wherein if the data is not contained in the cache then the method further comprises: searching the buffer to determine if data corresponding to the memory request is contained in the buffer and if so then promoting the data to the cache; and searching the table in order to determine if the address of the memory request matches any one of the entries in the PBVT and if so then clearing the table entry that matches the address of the memory request. 14. The method of claim 13, wherein searching the cache, the buffer and the table is done in parallel. 15. The method of claim 12, wherein if it is determined that the data corresponding to the prefetch address is not contained in one of a set of the cache and the buffer, and that the prefetch address is not contained in the table, then prefetching the data corresponding to the prefetch address and storing the prefetch address along with the corresponding data in the buffer. 16. The method of claim 13, wherein if it is determined that the buffer is full, then using a replacement algorithm to evict an entry in the buffer and to store the address of the evicted entry of the buffer in the table. 17. A method to create a table comprising: determining if a prefetch address is contained within one of a set of a cache and a buffer; if the prefetch address is not contained within either one of the set of the cache and the buffer, then retrieving a data stored at the prefetch address and storing the data along with the address in the buffer; if the buffer is full, then, using a replacement algorithm, evicting an entry of the buffer and replacing the evicted entry with the prefetch address along with the data; and storing the address of the evicted entry in the table. 18. The method of claim 17, wherein prior to determining if a prefetch address is contained within one of a set of a cache and a buffer the method further comprises: receiving a memory request from a processor, the request including an address of a data located in a memory; using a prefetching technique, predicting the prefetch address based on the address of the memory request. 19. The method of claim 18, wherein if it is determined that the address of the memory request is contained within the table, then clearing the table entry containing the address of the memory request. 20. The method of claim 18, wherein the prefetching technique is an inline prefetching technique. 21. The method of claim 17, wherein the replacement algorithm is a least recently used replacement algorithm. 22. The method of claim 18, wherein after receiving the memory request from the processor, the method further comprises: searching the cache for the requested data and if the requested data is not found in the cache then searching the buffer for the requested data and if the requested data is not found in the buffer then retrieving the requested data from the memory and storing the data along with the address in the cache; and searching the table for an entry matching the address of the requested data and if a match is found then clearing the table entry that matches the address of the requested data. 23. A computer system comprising: a processor; a memory coupled to the processor; a cache coupled to the processor, the cache to store a plurality of cache lines; and a controller coupled to the processor, the memory and the cache, the controller to determine whether a prefetch address tag is contained in a buffer and the cache, the controller comprises: a table to store a plurality of prefetch address tags, and a table controller to generate the prefetch address tag, the table controller searches the table for the prefetch address tag and will prefetch a data corresponding to the prefetch address tag if the prefetch address tag is not contained in the table. 24. The computer system of claim 23, wherein the table controller stores the data corresponding to the prefetch address tag in the buffer, and if the buffer is full then the table controller evicts a previously prefetched data and then stores the data corresponding to the prefetch address tag. 25. The computer system of claim 24, wherein the table controller evicts the previously prefetched data according to a replacement algorithm such as a least recently used replacement algorithm. 26. The computer system of claim 23, wherein the controller comprises a prefetch controller. 27. The computer system of claim 23, wherein the buffer evicts a previously prefetched data according to a replacement algorithm such as a least recently used replacement algorithm. 28. A computer-readable medium including one or more software modules to: predict a prefetch address and search a cache memory for a data corresponding to the prefetch address; to search a buffer for the data corresponding to the prefetch address if the prefetch address is not found in the cache; to retrieve the data corresponding to the prefetch address, to evict an entry of the buffer, and to replace the evicted entry with the prefetch address along with the data if the prefetch address is not found in the buffer; and to store the address of the evicted entry in a table. 29. The computer-readable medium of claim 28, wherein said one or more software modules to monitor the processor for a request to fetch data from a memory address and after the request is detected, to use a prefetching technique to predict the prefetch address. 30. The computer-readable medium of claim 28, wherein said one or more software modules to evict a previously prefetched data from the buffer according to a replacement algorithm such as a least recently used replacement algorithm. 31. The computer-readable medium of claim 29, wherein said one or more software modules to fetch data from the memory address, and to determine if the memory address is contained in the table and if it is to clear the entry. t al., 709/315