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Methods for planarization of non-planar surfaces in device fabrication 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/31
출원번호 US-0165263 (2002-06-06)
발명자 / 주소
  • Marsh, Eugene P.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 57  인용 특허 : 64

초록 ▼

A method of planarizing a surface of a wafer includes providing a planarization material on the wafer surface and bringing a substantially flat surface into contact with the planarization material on the wafer. The planarization material is exposed to radiation at a first wavelength to cure the plan

대표청구항 ▼

A method of planarizing a surface of a wafer includes providing a planarization material on the wafer surface and bringing a substantially flat surface into contact with the planarization material on the wafer. The planarization material is exposed to radiation at a first wavelength to cure the plan

이 특허에 인용된 특허 (64)

  1. Choinski Edward J. (Wayland MA), Apparatus and method for temporarily sealing holes in printed circuit boards.
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  4. Schwalm Reinhold (Wachenheim DEX) Binder Horst (Lampertheim DEX), Aqueous developer solution having hydroxy-alkyl piperidine for positive-working photoresists.
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  5. McGinniss Vincent D. (Sunbury OH) White James L. (Columbus OH) Mikuni Hiroyuki (Sagamihara JPX), Bimodal cured intermixed polymeric networks which are stable at high temperature.
    상세보기
  6. Shendon Norman (San Carlos CA), Chemical mechanical polishing apparatus with improved carrier and method of use.
    상세보기
  7. Shimomura Mariko (Yokohama JPX) Miyashita Naoto (Yokohama JPX) Ohashi Hiroyuki (Kamakura JPX), Chemical-mechanical polishing (CMP) method for controlling polishing rate using ionized water, and CMP apparatus.
    상세보기
  8. Chen Lai-Juh (Hsin-Chu TWX), Chemical/mechanical polish (CMP) thickness monitor.
    상세보기
  9. Sandhu Gurtej S. (Boise ID) Yu Chang (Boise ID) Doan Trung T. (Boise ID) Tuttle Mark E. (Boise ID), Conductive contact plug and a method of forming a conductive contact plug in an integrated circuit using laser planariza.
    상세보기
  10. Bunch Jesse C. (Silver Spring MD), Cube press.
    상세보기
  11. Blalock Guy T. ; Stroupe Hugh E. ; Gordon Brian F., Deadhesion method and mechanism for wafer processing.
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  12. Blalock, Guy T.; Stroupe, Hugh E.; Gordon, Brian F., Deadhesion method and mechanism for wafer processing.
    상세보기
  13. Prybyla Judith Ann ; Taylor Gary Newton, Device fabrication involving planarization.
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  14. Prybyla Judith Ann, Device fabrication involving surface planarization.
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  15. Weling Milind G. (San Jose CA) Bothra Subhas (San Jose CA) Gabriel Calvin T. (Cupertino CA), Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing.
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  16. Blalock Guy, Global planarization method and apparatus.
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  17. Blalock Guy, Global planarization method and apparatus.
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  18. Blalock Guy, Global planarization method and apparatus.
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  19. Allman Derryl D. J. (Colorado Springs CO) Fuchs Kenneth P. (Colorado Springs CO), Global planarization using SOG and CMP.
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  20. Miyashita Akimi (Toride JPX) Fujii Mutsumasa (Ibaraki-ken JPX) Mishina Haruo (Ushiku JPX), Hot press with pressure vessels to uniformly distribute pressure to the work piece.
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  21. Sandhu Gurtej S. (Boise ID) Yu Chris C. (Austin TX), IC chemical mechanical planarization process incorporating slurry temperature control.
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  22. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
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  23. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
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  24. Yu Chris C. (Boise ID) Sandhu Gurtej S. (Boise ID) Doan Trung T. (Boise ID), Integrated circuit polishing method.
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  25. Chou Richard Tien-Hua (Wilmington DE), Ionomers based on copolymers of ethylene with both mono-and dicarboxylic acids.
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  26. Tuttle Mark E. (Boise ID) Doan Trung T. (Boise ID) Fox Angus C. (Boise ID) Sandhu Gurtej S. (Boise ID) Stroupe Hugh E. (Boise ID), Method and apparatus for improving planarity of chemical-mechanical planarization operations.
    상세보기
  27. Hamamura Fumio (Kanagawa JPX) Oka Yukio (Yamaguchi JPX), Method and apparatus for pressure sticking a thin film to a base plate.
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  28. Reavill Joseph A. (Mira Loma CA) Arachi John M. (Riverside CA), Method and apparatus for vacuum lamination of flex circuits.
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  29. Tsunoda Kazuyoshi (Yuki JPX) Tonoki Kenji (Yuki JPX) Yokono Haruki (Yuki JPX) Kono Hisao (Yuki JPX) Yokoyama Ryoji (Musashino JPX) Kobayashi Kazuo (Shimodate JPX), Method and device for manufacturing a laminated material.
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  30. Blalock, Guy T.; Stroupe, Hugh E.; Carroll, Lynn J., Method for applying uniform pressurized film across wafer.
    상세보기
  31. Joseph A Levert ; Daniel Lynne Towery ; Denis Endisch, Method for integrated circuit planarization.
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  32. Paranjpe Ajit P. (Plano TX), Method for planarization.
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  33. Dawson Robert (Austin TX) Ponder Kenneth J. (Las Gatos CA), Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical pol.
    상세보기
  34. Kim Sung C. (Boise ID) Meikle Scott (Boise ID), Method for shaping features of a semiconductor structure using chemical mechanical planarization (CMP).
    상세보기
  35. Hayashi Yoshihiro (Tokyo JPX), Method of flattening the surface of a semiconductor device by polishing.
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  36. Blalock Guy (Boise ID) Wald Phillip G. (Boise ID), Method of forming a stacked capacitor with striated electrode.
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  37. J. Mike Brooks ; Jerrold L. King ; Kevin Schofield, Method of forming an integrated circuit device having cyanate ester buffer coat.
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  38. Tola Jeffry (Morrison IL), Method of making diaphragm-type pressure transducers.
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  39. Tuttle Mark E. ; Doan Trung Tri, Method of passivating semiconductor wafers.
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  40. Matsuda Tetsuo (Poughkeepsie NY) Okumura Katsuya (Poughkeepsie NY), Method of planarizing a semiconductor workpiece surface.
    상세보기
  41. Schwarzbauer Herbert (Munich DEX), Method of securing electronic components to a substrate.
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  42. Lowrey Tyler A. (Boise ID) Doan Trung T. (Boise ID) Cathey David A. (Boise ID) Rolfson J. Brett (Boise ID), Method to form high aspect ratio supports (spacers) for field emission display using micro-saw technology.
    상세보기
  43. Doan Trung T. (Boise ID) Yu Chris C. (Boise ID), Multiple step method of chemical-mechanical polishing which minimizes dishing.
    상세보기
  44. Kudo Takanori (Sayama JPX) Masuda Seiya (Tokorozawa JPX) Kinoshita Yoshiaki (Tokyo JPX) Przybilla Klaus (Frankfurt DEX) Endo Natsumi (Kawagoe JPX) Suehiro Natsumi (Kawagoe JPX) Okazaki Hiroshi (Kawag, Pattern forming material including photoacid and photobase generators for large exposure latitude.
    상세보기
  45. Eugene P. Marsh, Planarization of non-planar surfaces in device fabrication.
    상세보기
  46. Marsh Eugene P., Planarization of non-planar surfaces in device fabrication.
    상세보기
  47. Doan Trung T. ; Blalock Guy T. ; Durcan Mark ; Meikle Scott G., Planarization process for semiconductor substrates.
    상세보기
  48. Stroupe Hugh (Boise ID) Sharan Sujit (Boise ID) Sandhu Gurtej S. (Boise ID), Polishing apparatus, a polishing wafer carrier apparatus, a replacable component for a particular polishing apparatus an.
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  49. Katakabe Ichiro (Kanagawa-ken JPX) Miyashita Naoto (Kanagawa-ken JPX) Akiyama Tatsuo (Tokyo JPX), Polishing method and apparatus for detecting a polishing end point of a semiconductor wafer.
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  50. Robinson Karl M. (Boise ID), Polishing pad and a method for making a polishing pad with covalently bonded particles.
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  51. Talieh Homayoun (San Jose CA) Weldon David E. (Los Gatos CA), Polishing pad cluster for polishing a semiconductor wafer.
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  52. Karlsrud Chris (Chandler AZ), Polishing pad conditioning.
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  53. Winkle Mark Robert (Lansdale PA), Positive acting photoresist comprising a photoacid, a photobase and a film forming acid-hardening resin system.
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  54. Namysl Edmond (1907 Frederick Placentia CA 92670), Printed circuit board laminating machine.
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  55. Jacob Adir (23 Juniper La. Framingham MA 01701), Process for dry sterilization of medical devices and materials.
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  56. Richard Alden DeFelice ; Judith Prybyla, Process for planarization a semiconductor substrate.
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  57. Nagashima Naoki (Kanagawa JPX) Takahashi Hiroshi (Kanagawa JPX), Process for planarizing surface of a semiconductor device.
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  58. Padmanaban Munirathna,JPX ; Kinoshita Yoshiaki,JPX ; Okazaki Hiroshi,JPX ; Masuda Seiya,JPX ; Kawasaki Natsumi,JPX ; Funato Satoru,JPX ; Pawlowski Georg,JPX, Radiation-sensitive composition containing plasticizer.
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  59. Roeschert Horst (Ober-Hilbersheim DEX) Pawlowski Georg (Wiesbaden DEX) Przybilla Klaus-Juergen (Frankfurt am Main DEX), Radiation-sensitive mixture with a polymeric binder containing units of ab.
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  60. Bose Amitava (Nashua NH) Garver Marion M. (Marlborough MA) Nasr Andre I. (Marlborough MA) Cooperman Steven S. (Southborough MA), Shallow trench isolation process for high aspect ratio trenches.
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  61. Blalock Guy (Boise ID) Wald Phillip G. (Boise ID), Stacked capacitor construction.
    상세보기
  62. Iijima Nobuo (Kawasaki JPX) Hayashida Akihisa (Kawasaki JPX), Tape-on-wafer mounting apparatus and method.
    상세보기
  63. Pasch Nicholas F. (Pacifica CA) Mallon Thomas G. (Santa Clara CA) Franklin Mark A. (Scott\s Valley CA), Techniques for assembling polishing pads for chemi-mechanical polishing of silicon wafers.
    상세보기
  64. Clover Richmond B. (1199 W. Vanderbilt Ct. Sunnyvale CA 94087), Vertically stacked planarization machine.
    상세보기

이 특허를 인용한 특허 (57)

  1. Sreenivasan, Sidlgata V; Watts, Michael P. C.; Choi, Byung J.; Voisin, Ronald D., Alignment methods for imprint lithography.
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  2. Sreenivasan,Sidlgata V; Watts,Michael P. C.; Choi,Byung Jin; Voisin,Ronald D.; Schumaker,Norman E., Alignment systems for imprint lithography.
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  3. Choi,Byung Jin; Sreenivasan,Sidlgata V.; Johnson,Stephen C., Apparatus to control displacement of a body spaced-apart from a surface.
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  4. McCutcheon, Jeremy; Lamb, III, James E., Automated process and apparatus for planarization of topographical surfaces.
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  5. Choi,Byung J.; Voisin,Ronald D.; Sreenivasan,Sidlgata V.; Watts,Michael P. C.; Babbs,Daniel; Meissl,Mario J.; Bailey,Hillman; Schumaker,Norman E., Chucking system for modulating shapes of substrates.
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  6. Xu,Frank Y.; Miller,Michael N.; Watts,Michael P. C., Composition for an etching mask comprising a silicon-containing material.
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  7. McCutcheon, Jeremy W.; Brown, Robert D., Contact planarization apparatus.
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  8. Sreenivasan, Sidlgata V.; Choi, Byung J.; Colburn, Matthew; Bailey, Todd, Dual wavelength method of determining a relative position of a substrate and a template.
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  9. Choi, Byung J.; Sreenivasan, Sidlgata V., Flexure based macro motion translation stage.
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  10. Choi, Byung Jin; Meissl, Mario J.; Sreenivasan, Sidlagata V.; Watts, Michael P. C., Formation of discontinuous films during an imprint lithography process.
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  11. Choi,Byung Jin; Meissl,Mario J.; Sreenivasan,Sidlagata V.; Watts,Michael P. C., Formation of discontinuous films during an imprint lithography process.
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  12. Choi, Byung Jin; Sreenivasan, Sidlgata V.; Johnson, Stephen C., High precision orientation alignment and gap control stages for imprint lithography processes.
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  13. Sreenivasan, S. V.; Choi, Byung J.; Colburn, Matthew; Bailey, Todd, High resolution overlay alignment systems for imprint lithography.
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  14. Sreenivasan, Sidlgata V.; Choi, Byung J.; Colburn, Matthew; Bailey, Todd, High-resolution overlay alignment methods for imprint lithography.
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  15. Sreenivasan, Sidlgata V.; Choi, Byung J.; Colburn, Matthew; Bailey, Todd, Imprint lithography template comprising alignment marks.
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  16. Sreenivasan,Sidlgata V.; Schumaker,Philip D., Imprint lithography template having opaque alignment marks.
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  17. Sreenivasan, Sidlgata V.; Choi, Byung-Jin, Imprinting of partial fields at the edge of the wafer.
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  18. Xu, Frank Y.; Watts, Michael P. C.; Stacey, Nicholas A., Materials for imprint lithography.
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  19. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Method and system for double-sided patterning of substrates.
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  20. Choi, Byung J.; Sreenivasan, Sidlgata V., Method for determining characteristics of substrate employing fluid geometries.
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  21. Watts,Michael P. C.; Sreenivasan,Sidlgata V., Method for fabricating bulbous-shaped vias.
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  22. Willson, Carlton Grant; Sreenivasan, Sidlgata V.; Bonnecaze, Roger T., Method for fabricating nanoscale patterns in light curable compositions using an electric field.
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  23. Sreenivasan, Sidlgata V.; Bonnecaze, Roger T.; Willson, Carlton Grant, Method for imprint lithography using an electric field.
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  24. Choi, Byung J.; Voisin, Ronald D.; Sreenivasan, Sidlgata V.; Watts, Michael P. C.; Willson, C. Grant; Schumaker, Norman E.; Meissl, Mario J., Method for modulating shapes of substrates.
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  25. Stecher, Thomas E., Method for planarizing bumped die.
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  26. Sreenivasan,Sidlgata V.; Choi,Byung J.; Colburn,Matthew; Bailey,Todd, Method of aligning a template with a substrate employing moire patterns.
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  27. Choi, Byung-Jin; Sreenivasan, Sidlgata V.; Willson, Carlton Grant; Colburn, Mattherw E.; Bailey, Todd C.; Ekerdt, John G., Method of automatic fluid dispensing for imprint lithography processes.
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  28. Sreenivasan, Sidlgata V.; McMackin, Ian M.; Melliar-Smith, Christopher Mark; Choi, Byung-Jin, Method of concurrently patterning a substrate having a plurality of fields and a plurality of alignment marks.
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  29. Bailey,Todd; Choi,Byung J.; Colburn,Matthew; Sreenivasan,Sidlgata V.; Willson,C. Grant; Ekerdt,John, Method of creating a dispersion of a liquid on a substrate.
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  30. Marsh,Eugene P., Method of forming a catalytic surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms.
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  31. Marsh, Eugene P., Method of forming a substrate having a surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms.
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  32. Sreenivasan,Sidlgata V., Method of forming stepped structures employing imprint lithography.
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  33. Choi,Byung Jin; Sreenivasan,Sidlgata V.; Johnson,Stephen C., Method of orientating a template with respect to a substrate in response to a force exerted on the template.
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  34. Rubin, Daniel I., Method of reducing pattern distortions during imprint lithography processes.
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  35. Sreenivasan, Sidlgata V.; Choi, Byung J.; Colburn, Matthew; Bailey, Todd, Method of varying template dimensions to achieve alignment during imprint lithography.
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  36. Sreenivasan, Sidlgata V.; Watts, Michael P. C., Method to arrange features on a substrate to replicate features having minimal dimensional variability.
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  37. Choi, Byung Jin; Sreenivasan, Sidlgata V.; Johnson, Stephen C., Method to control the relative position between a body and a surface.
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  38. Choi,Byung Jin; Xu,Frank Y.; Stacey,Nicholas A.; Truskett,Van Xuan Hong; Watts,Michael P. C., Method to reduce adhesion between a conformable region and a pattern of a mold.
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  39. Truskett,Van N.; Mackay,Christopher J.; Choi,B. Jin, Method to reduce adhesion between a polymerizable layer and a substrate employing a fluorine-containing layer.
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  40. Choi, Byung J.; Colburn, Matthew; Sreenivasan, S. V.; Willson, C. Grant; Bailey, Todd; Ekerdt, John, Methods for high-precision gap and orientation sensing between a transparent template and substrate for imprint lithography.
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  41. Voisin,Ronald D., Methods of manufacturing a lithography template.
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  42. Sreenivasan, Sidlgata V.; Schumaker, Philip D., Patterning a plurality of fields on a substrate to compensate for differing evaporation times.
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  43. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Patterning substrates employing multiple chucks.
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  44. Sreenivasan,Sidlgata V., Positive tone bi-layer imprint lithography method.
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  45. Watts,Michael P. C.; McMackin,Ian, Scatterometry alignment for imprint lithography.
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  46. Schmid, Gerard M.; Stacey, Nicholas A; Resnick, Douglas J.; Voisin, Ronald D.; Myron, Lawrence J., Self-aligned process for fabricating imprint templates containing variously etched features.
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  47. Marsh, Eugene P.; Quick, Timothy A., Semiconductor processing.
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  48. Marsh, Eugene P.; Quick, Timothy A., Semiconductor processing.
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  49. McMackin,Ian M.; Stacey,Nicholas A.; Babbs,Daniel A.; Voth,Duane J.; Watts,Michael P. C.; Truskett,Van N.; Xu,Frank Y.; Voisin,Ronald D.; Lad,Pankaj B., Single phase fluid imprint lithography method.
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  50. Xu, Frank Y.; Khusnatdinov, Niyaz, Single phase fluid imprint lithography method.
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  51. Sreenivasan, Sidlgata V.; Choi, Byung J.; Schumaker, Norman E.; Voisin, Ronald D.; Watts, Michael P. C.; Meissl, Mario J., Step and repeat imprint lithography processes.
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  52. Sreenivasan,Sidlgata V.; Choi,Byung J.; Schumaker,Norman E.; Voisin,Ronald D.; Watts,Michael P. C.; Meissl,Mario J., Step and repeat imprint lithography processes.
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  53. Sreenivasan, Sidlgata V.; Watts, Michael P. C.; Choi, Byung Jin; Meissl, Mario J.; Schumaker, Norman E.; Voisin, Ronald D., Step and repeat imprint lithography systems.
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  54. Watts, Michael P. C.; Choi, Byung-Jin; Sreenivasan, Sidlgata V., System and method for dispensing liquids.
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  55. GanapathiSubramanian, Mahadevan; Choi, Byung-Jin; Miller, Michael N.; Stacey, Nicholas A., Technique for separating a mold from solidified imprinting material.
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  56. Selinidis, Kosta S.; Choi, Byung-Jin; Schmid, Gerard M.; Thompson, Ecron D.; McMackin, Ian Matthew, Template having alignment marks formed of contrast material.
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  57. Sreenivasan, Sidlgata V.; Schumaker, Philip D.; McMackin, Ian M., Tessellated patterns in imprint lithography.
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