IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0408580
(2003-04-08)
|
우선권정보 |
JP-0110903 (2002-04-12); JP-0110904 (2002-04-12) |
발명자
/ 주소 |
- Takedomi, Harumi
- Koike, Eiji
- Kousaka, Keishi
|
출원인 / 주소 |
- Honda Giken Kogyo Kabushiki Kaisha
|
대리인 / 주소 |
Armstrong, Westerman & Hattori, LLP
|
인용정보 |
피인용 횟수 :
12 인용 특허 :
4 |
초록
▼
A small battery box, in which arrangement of cells can be easily changed, for suppressing nonuniformity in temperature distribution between the cells. The box has a container having upper, lower, front, rear, and side portions which can be disassembled; a battery holder having members which are deta
A small battery box, in which arrangement of cells can be easily changed, for suppressing nonuniformity in temperature distribution between the cells. The box has a container having upper, lower, front, rear, and side portions which can be disassembled; a battery holder having members which are detachably connected in a manner such that central axes of the cells are parallel to a direction along which the side portions face each other and the cells are arranged in a zig-zag matrix form; a shielding member, near a coolant supply opening in the front portion, for changing the flow direction of the coolant and for preventing the coolant from directly blowing onto the cells; and a control member, near a coolant discharge opening in the rear portion, for changing the coolant flow direction in a manner such that the coolant flows towards the rear side of each cell near the discharge opening.
대표청구항
▼
A small battery box, in which arrangement of cells can be easily changed, for suppressing nonuniformity in temperature distribution between the cells. The box has a container having upper, lower, front, rear, and side portions which can be disassembled; a battery holder having members which are deta
A small battery box, in which arrangement of cells can be easily changed, for suppressing nonuniformity in temperature distribution between the cells. The box has a container having upper, lower, front, rear, and side portions which can be disassembled; a battery holder having members which are detachably connected in a manner such that central axes of the cells are parallel to a direction along which the side portions face each other and the cells are arranged in a zig-zag matrix form; a shielding member, near a coolant supply opening in the front portion, for changing the flow direction of the coolant and for preventing the coolant from directly blowing onto the cells; and a control member, near a coolant discharge opening in the rear portion, for changing the coolant flow direction in a manner such that the coolant flows towards the rear side of each cell near the discharge opening. aid second lower electrode second ferroelectric film and second upper electrode are combined to configure a second ferroelectric capacitor. 8. The semiconductor device according to claim 7, wherein said first semiconductor region is a source, said second semiconductor region is a drain and said gate electrode, source, drain and semiconductor substrate are combined to configure a cell transistor. 9. The semiconductor device according to claim 8, wherein a series connected TC unit type ferroelectric memory comprises series connected memory cells each having said cell transistor (T) having said source and said drain and said first ferroelectric capacitor (C) inbetween said source and said drain. 10. A semiconductor device comprising: a first semiconductor region formed in a surface region of a semiconductor substrate; a second semiconductor region formed separately from said first semiconductor region in said surface region of said semiconductor substrate; a gate insulating film formed on a portion of said semiconductor substrate which is arranged between said first and second semiconductor regions; a gate electrode formed on said gate insulating film; an interlayer insulating film formed on said semiconductor substrate to cover said first semiconductor region, second semiconductor region and gate electrode; first and second lower electrodes formed on said interlayer insulating film; a first contact plug formed in said interlayer insulating film and in contact with said first lower electrode; a second contact plug formed in said interlayer insulating film and in contact with said second lower electrode; a third contact plug formed in said interlayer insulating film and in contact with said first semiconductor region, said third contact plug being electrically connected to said first contact plug and said second contact plug; a first ferroelectric film formed on said first lower electrode; a first upper electrode formed on said first ferroelectric film; a second ferroelectric film formed on said second lower electrode; and a second upper electrode formed on said second ferroelectric film. 11. The semiconductor device according to claim 10, wherein said first and second lower electrodes are separately formed. 12. The semiconductor device according to claim 10, wherein said first and second lower electrodes are integrally formed. 13. The semiconductor device according to claim 12, wherein said first and second ferroelectric films are integrally formed. 14. The semiconductor device according to claim 10, wherein said first upper electrode is connected to said second semiconductor region. 15. The semiconducter device according to claim 10, wherein said first lower electrodes, first ferroelectric film and first upper electrode are combined to configure a first ferroelectric capacitor and said second lower electrode, second ferroelectric film and second upper electrode are combined to configure a second ferroelectric capacitor. 16. The semiconductor device according to claim 15, wherein said first semiconductor region is a source, said second semiconductor region is a drain and said gate electrode, source, drain and semiconductor substrate are combined to configure a cell transistor. 17. The semiconductor device according to claim 16, wherein a series connected TC unit type ferroelectric memory comprises series connected memory cells each having said cell transistor (T) having said source and said drain and said first ferroelectric capacitor (C) inbetween said source and said drain. 18. A semiconductor device comprising: a first semiconductor region formed in a surface region of a semiconductor substrate; a second semiconductor region formed separately from said first semiconductor region in said surface region of said semiconductor substrate; a gate insulating film formed on a portion of said semiconductor substrate which is arranged between said first semiconductor region and said second semiconductor region; a
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