초록 ▼

A demodulator used in a base band processor of the spread spectrum radio transceiver includes a demodulator circuit for spread spectrum phase shift keying (PSK) demodulating an information signal received from a radio circuit. The information signal includes data symbols formed from a plurality of h

A demodulator used in a base band processor of the spread spectrum radio transceiver includes a demodulator circuit for spread spectrum phase shift keying (PSK) demodulating an information signal received from a radio circuit. The information signal includes data symbols formed from a plurality of high rate mode chips forming a spread spectrum information signal. At least one predetermined code function correlator is in line with a signal input for decoding the information signal according to a predetermined code. A carrier loop circuit allows phase and frequency tracking of the information signal and a chip decision circuit is operative with the carrier loop circuit for tracking high rate mode chips. A decision feedback equalizer formed from a feedback finite impulse response filter is operative with the chip decision circuit and the carrier loop circuit. It has a plurality of feedback taps. At least one feedback tap is selected for logical add/subtract operations to aid in canceling multipath signal echoes. A feed forward finite impulse response filter can also be positioned in line to the code function correlator and the signal input and has a plurality of feed forward taps that are selected for logical multiply operations to aid in reducing multipath signal echoes. A method aspect of the invention is also disclosed.

대표청구항 ▼

A demodulator used in a base band processor of the spread spectrum radio transceiver includes a demodulator circuit for spread spectrum phase shift keying (PSK) demodulating an information signal received from a radio circuit. The information signal includes data symbols formed from a plurality of h

A demodulator used in a base band processor of the spread spectrum radio transceiver includes a demodulator circuit for spread spectrum phase shift keying (PSK) demodulating an information signal received from a radio circuit. The information signal includes data symbols formed from a plurality of high rate mode chips forming a spread spectrum information signal. At least one predetermined code function correlator is in line with a signal input for decoding the information signal according to a predetermined code. A carrier loop circuit allows phase and frequency tracking of the information signal and a chip decision circuit is operative with the carrier loop circuit for tracking high rate mode chips. A decision feedback equalizer formed from a feedback finite impulse response filter is operative with the chip decision circuit and the carrier loop circuit. It has a plurality of feedback taps. At least one feedback tap is selected for logical add/subtract operations to aid in canceling multipath signal echoes. A feed forward finite impulse response filter can also be positioned in line to the code function correlator and the signal input and has a plurality of feed forward taps that are selected for logical multiply operations to aid in reducing multipath signal echoes. A method aspect of the invention is also disclosed. ubo et al., 365/227 ck is coupled to a respective bottom bit line; positioning a plurality of sense amplifiers between the top block of data cells and the bottom block of data cells, each sense amplifier of the plurality of sense amplifiers is shared by a respective top bit line and a respective bottom bit line; when a first data cell in the top block is accessed, activating a first replica memory cell with a maximum driving strength of a portion of driving strength of each of the data cells in the top block and the bottom block of data cells for discharging a first respective bottom bit line at a portion of a discharge rate of a first respective top bit line driven by the accessed first data cell, and comparing the charge on a first respective top bit line driven by the accessed first data cell and the charge on the first respective bottom bit line driven by the first replica memory cell by a first respective sense amplifier to determine the state of the accessed data cell in the top block in response to portioned discharge rate of the first respective bottom bit line; when a second data cell in the bottom block is accessed, activating a second replica memory cell a maximum driving strength of a portion of driving strength of each of the data cells in the top block and the bottom block of data cells for discharging a second respective top bit line at a portion of a discharge rate of a second respective bottom bit line driven by the accessed second data cell, and comparing the charge on a second respective bottom bit line driven by the accessed second data cell and the charge on the second respective top bit line driven by the second replica memory cell by a second respective sense amplifier to determine the state of the accessed data cell in the bottom block in response to portioned discharge rate of the second respective top bit line; and equalizing a write bit line in the top block of data cells with a respective write bit line in the bottom block of data cells during a read cycle. 9. The method of claim 8, wherein the portion of driving strength of the first replica memory cell and the second replica memory cell is one-half of driving strength of each of the data cells in the top block and the bottom block of data cells. 10. The method of claim 8, wherein each data cell in the top block and the bottom block of data cells comprises of three transistors. 11. The method of claim 8, wherein each data cell in the top block and the bottom block of data cells uses same layout rules. 12. The method of claim 8, wherein each respective top bit line and each respective bottom bit line have same diffusion capacitance. 13. The method of claim 8, further comprising the step of coupling a read line in the top block of data cells with a respective read line in the bottom block of data cells before a read cycle for read cycle equalization. 14. The method of claim 8, further comprising the step of limiting voltage swing on the respective global bit line for read and write cycles by a transistor gate coupled between a respective local bit line and a respective global bit line. 15. A DRAM comprising: a first block of data cells including a plurality of data cell arrays, wherein each of the data cell arrays includes a plurality of data cells; a second block of data cells including a plurality of data cell arrays, wherein each of the data cell arrays includes a plurality of data cells; a sense amplifier array positioned between the first block of data cells and the second block of data cells, each sense amplifier in the sense amplifier array is shared by a respective data cell array in the first block and a respective data cell array in the second block; a first replica memory cell with a maximum driving strength of a portion of driving strength of each of the data cells in the first block and the second block of data cells, wherein when a first data cell in the first block is accessed, the first replica memory cell discharges a first respective bit li