IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0618738
(2000-07-18)
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발명자
/ 주소 |
- Ellison, Carl M.
- Golliver, Roger A.
- Herbert, Howard C.
- Lin, Derrick C.
- McKeen, Francis X.
- Neiger, Gilbert
- Reneris, Ken
- Sutton, James A.
- Thakkar, Shreekant S.
- Mittal, Millind
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출원인 / 주소 |
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대리인 / 주소 |
Blakley, Sokoloff, Taylor & Zafman LLP
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인용정보 |
피인용 횟수 :
107 인용 특허 :
56 |
초록
▼
The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is
The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated area of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that contains configuration settings related to a page and access information. An access checking circuit coupled to the configuration storage checks the access transaction using at least one of the configuration settings and the access information and generates an access grant signal if the access transaction is valid.
대표청구항
▼
The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is
The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated area of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that contains configuration settings related to a page and access information. An access checking circuit coupled to the configuration storage checks the access transaction using at least one of the configuration settings and the access information and generates an access grant signal if the access transaction is valid. is associated with a plurality of data registers such that the address register can specify an operation to be performed on a plurality of portions of data words. 12. The method of claim 1 further comprising incrementing the address register while the portion of the data word is being processed. 13. An apparatus for processing data words in a processing system comprising: at least one data register for temporarily storing a data word to be processed; at least one address register associated with the data register, the address register temporarily storing an address word associated with a portion of the data word to be processed and containing information related to the portion of the data word to be processed, said information identifying a data type of the portion of the data word; and a processor for processing the portion of the data word using the information in the address register. 14. The apparatus of claim 13 wherein the information identifies the size of the portion of the data word. 15. The apparatus of claim 13 wherein the information identifies a number of bits in the portion of the data word. 16. The apparatus of claim 13 wherein the information identifies a number of bytes in the portion of the data word. 17. The apparatus of claim 13 wherein the information identifies the position of the portion of the data word within the data word. 18. The apparatus of claim 13 wherein the data type is one of signed and unsigned data. 19. The apparatus of claim 13 wherein the processor, in processing the portion of the data word, extracts the portion of the data word from the data word using the information in the address register. 20. The apparatus of claim 19 further comprising a shifter for shifting the portion of the data word into a predetermined position in the data word using the information in the address register to extract the portion of the data word from the data word. 21. The apparatus of claim 19 wherein the processor, in processing the portion of the data word, inserts the portion of the data word into the data word to form the data word using the information in the address register. 22. The apparatus of claim 13 wherein the processor, in processing the portion of the data word, inserts the portion of the data word into the data word to form the data word using the information in the address register. 23. The apparatus of claim 13 wherein the apparatus is part of a SIMD system in which the address register is associated, with a plurality of data registers such that the address register can specify an operation to be performed on a plurality of portions of data words. 24. The apparatus of claim 13 wherein the address register is incrementable while the portion of the data word is being processed. US-5754759, 19980500, Clarke et al., 714/037; US-5761706, 19980600, Kessler et al., 711/118; US-5798693, 19980800, Engellenner, 340/010.33; US-5860136, 19990100, Fenner, 711/201; US-5867799, 19990200, Lang et al., 707/001; US-5948073, 19990900, Chapin et al., 710/001; US-5954793, 19990900, Stutman et al., 709/204; US-6057756, 20000500, Engellenner, 340/505; US-6108657, 20000800, Shoup et al., 707/100; US-6308220, 20011000, Mathur, 709/238; US-6421790, 20020700, Fruehling et al., 714/030; US-6553466, 20030400, Friedman et al., 711/152
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