초록 ▼

A terminated input string with symbols is split with timing control into at least two input sequences. The input sequences are each individually encoded with an outer code to form output sequences. The output sequences are combined symbol-by-symbol into an output string with symbols. The output stri

A terminated input string with symbols is split with timing control into at least two input sequences. The input sequences are each individually encoded with an outer code to form output sequences. The output sequences are combined symbol-by-symbol into an output string with symbols. The output string is then encoded with an inner code.

대표청구항 ▼

A terminated input string with symbols is split with timing control into at least two input sequences. The input sequences are each individually encoded with an outer code to form output sequences. The output sequences are combined symbol-by-symbol into an output string with symbols. The output stri

A terminated input string with symbols is split with timing control into at least two input sequences. The input sequences are each individually encoded with an outer code to form output sequences. The output sequences are combined symbol-by-symbol into an output string with symbols. The output string is then encoded with an inner code. l response data generated by each of said at least two of said semiconductor devices in response to said test data. 13. The probe card assembly of claim 12 further comprising comparing means for comparing said expected response data received from said tester with said actual response data read from each of said at least two semiconductor devices. 14. The probe card assembly of claim 13 further comprising transmitting means for transmitting through said tester interface means a result of said comparison of said expected response data received from said tester with said actual response data read from each of said at least two of said semiconductor devices. 15. The probe card assembly of claim 13 further comprising memory means for storing a result of said comparison of said expected response data received from said tester with said actual response data read from each of said at least two of said semiconductor devices. 16. A method of testing a plurality of semiconductor devices comprising: generating at a semiconductor tester test data and location data identifying a location on one of said semiconductor devices; transmitting said test data and said location data to a probe card assembly; writing said test data from said probe card assembly to said location on at least two of said semiconductor devices; generating at said semiconductor tester expected response data; transmitting said expected response data to said probe card assembly; and reading at said probe card assembly actual response data from each of said at least two of said semiconductor devices. 17. The method of claim 16 further comprising comparing at said probe card assembly said expected response data received with said actual response data read from each of said at least two semiconductor devices. 18. The method of claim 17 further comprising transmitting from said probe card assembly to said semiconductor tester a result of said comparison of said expected response data with said actual response data read from each of said at least two of said semiconductor devices. 19. The method of claim 17 further comprising storing at said probe card assembly a result of said comparison of said expected result data with said actual result data read from each of said at least two of said semiconductor devices. 20. The method of claim 16, wherein said plurality of semiconductor devices are in unsingulated wafer form.