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Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/30
  • H01L-021/46
  • H01L-021/84
  • H01L-021/00
출원번호 US-0178542 (2002-06-25)
발명자 / 주소
  • Maszara, Witold P.
출원인 / 주소
  • Advanced Micro Devices, Inc.
인용정보 피인용 횟수 : 109  인용 특허 : 12

초록

A silicon-on-insulator (SOI) device with a strained silicon film has a substrate, and a buried oxide layer on the substrate. Silicon islands are formed on the buried oxide layer, the silicon islands being separated from each other by gaps. The buried oxide layers has recesses directly under the gaps

대표청구항

1. A method of forming strained device film, comprising the steps of: etching recesses in a buried oxide layer of a silicon-on-insulator (SOI) structure having a substrate, a buried oxide layer on the substrate, and a silicon layer on the buried oxide layer, the silicon layer having trenches, and

이 특허에 인용된 특허 (12)

  1. Houston Theodore W., Buried oxide with a thermal expansion matching layer for SOI.
  2. Candelaria Jon J. (Tempe AZ), Enhanced mobility MOSFET device and method.
  3. Sobczak Zbigniew P. (Colorado Springs CO), Formation and planarization of silicon-on-insulator structures.
  4. Geissler Stephen Frank ; Voldman Steven Howard, Method and structure for SOI wafers to avoid electrostatic discharge.
  5. Matthias Forster DE; Jorn Lutzen DE; Martin Gutsche DE; Anja Morgenschweis DE, Method for fabricating a trench capacitor.
  6. Xiang, Qi; Fisher, Philip A., Method for shallow trench isolation using passivation material for trench bottom liner.
  7. Scharf, Bruce R.; Kubby, Joel A.; Lin, Chuang-Chia; Tran, Alex T.; Zosel, Andrew J.; Gulvin, Peter M.; Chen, Jingkuang, Process for manufacturing micromechanical and microoptomechanical structures with backside metalization.
  8. Nivo Rovedo ; Chung Hon Lam, Self-aligned junction isolation.
  9. Sun Shih-wei,TWX, Silicon on insulator (SOI) dram cell structure and process.
  10. Noble Wendell P., Silicon-on-insulator islands.
  11. Carl J. Radens ; Gary B. Bronner ; Tze-chiang Chen ; Bijan Davari ; Jack A. Mandelman ; Dan Moy ; Devendra K. Sadana ; Ghavam Ghavami Shahidi ; Scott R. Stiffler, Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap.
  12. Hemmenway Donald F. (Melbourne FL) Gaul Stephen J. (Melbourne FL) McCarty Chris A. (Melbourne FL), Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure.

이 특허를 인용한 특허 (109)

  1. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  3. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  4. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  5. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  6. Currie,Matthew T., Control of strain in device layers by prevention of relaxation.
  7. Currie,Matthew T., Control of strain in device layers by selective relaxation.
  8. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  9. Wu,Kenneth C.; Fitzgerald,Eugene A.; Taraschi,Gianni; Borenstein,Jeffrey T., Etch stop layer system.
  10. Lauer, Isaac; Majumdar, Amlan; Solomon, Paul M.; Koester, Steven J., Fabrication of a vertical heterojunction tunnel-FET.
  11. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  18. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  19. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  20. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  21. Doris, Bruce B.; Chidambarrao, Dureseti; Baie, Xavier; Mandelman, Jack A.; Sadana, Devendra K.; Schepis, Dominic J., Field effect transistor with stressed channel and method for making same.
  22. Shaheen,Mohamad A.; Doyle,Brian; Dutta,Suman; Chau,Robert S.; Tolchinsky,Peter, High mobility tri-gate devices and methods of fabrication.
  23. Currie, Matthew T., Hybrid fin field-effect transistor structures and related methods.
  24. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  25. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  26. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  27. Chang,Peter L. D.; Doyle,Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  28. Doyle,Brian S.; Chang,Peter L. D., Independently accessed double-gate and tri-gate transistors in same process flow.
  29. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
  30. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  31. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  32. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  33. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  34. Cheng,Zhiyuan; Fitzgerald,Eugene A.; Antoniadis,Dimitri A., Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers.
  35. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
  36. Change, Peter L. D., Method of forming a transistor having gate protection and transistor formed according to the method.
  37. Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
  38. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  39. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  40. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.
  41. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming III-V semiconductor device structures.
  42. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain.
  43. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes.
  44. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  45. Currie,Matthew T., Methods of forming hybrid fin field-effect transistor structures.
  46. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods of forming strained-semiconductor-on-insulator device structures.
  47. Lochtefeld,Anthony J.; Langdo,Thomas A.; Hammond,Richard; Currie,Matthew T.; Braithwaite,Glyn; Fitzgerald,Eugene A., Methods of forming strained-semiconductor-on-insulator finFET device structures.
  48. Shaheed,M. Reaz; Hoffmann,Thomas; Armstrong,Mark; Auth,Christopher P., Methods of manufacturing a stressed MOS transistor structure.
  49. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
  50. Doyle, Brian S.; Datta, Suman; Jin, Been Yih; Chau, Robert, Non-planar MOS structure with a strained channel region.
  51. Doyle,Brian S.; Datta,Suman; Jin,Been Yih; Chau,Robert, Non-planar MOS structure with a strained channel region.
  52. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
  53. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  54. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  55. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  56. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  57. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  58. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  59. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  60. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  61. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  62. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  63. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  64. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  65. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  66. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  67. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  68. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  69. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  70. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  71. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.
  72. Agnello, Paul D.; Bedell, Stephen W.; Dennard, Robert H.; Domenicucci, Anthony G.; Fogel, Keith E.; Sadana, Devendra K., Relaxed low-defect SGOI for strained SI CMOS applications.
  73. Agnello, Paul D.; Bedell, Stephen W.; Dennard, Robert H.; Domenicucci, Anthony G.; Fogel, Keith E.; Sadana, Devendra K., Relaxed, low-defect SGOI for strained Si CMOS applications.
  74. Agnello,Paul D.; Bedell,Stephen W.; Dennard,Robert H.; Domenicucci,Anthony G.; Fogel,Keith E.; Sadana,Devendra K., Relaxed, low-defect SGOI for strained Si CMOS applications.
  75. Chang, Peter L. D.; Doyle, Brian S., Self-aligned contacts for transistors.
  76. Uchida, Hidetsugu, Semiconductor device and manufacturing method thereof.
  77. Cheng, Zhiyuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A., Semiconductor device structure.
  78. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  79. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  80. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  81. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  82. Fanelli, Stephen A., Semiconductor device with self-aligned back side features.
  83. Chi,Min Hwa; Yeo,Yee Chia; Hu,Chenming, Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials.
  84. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  85. Xiang,Qi; Subba,Niraj; Maszara,Witold P.; Krivokapic,Zoran; Lin,Ming Ren, Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor.
  86. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained germanium-on-insulator device structures.
  87. Huang, Chien-Chao; Huang, Cheng-Chuan; Yang, Fu-Liang, Strained silicon device.
  88. Huang,Chien Chao; Huang,Cheng Chuan; Yang,Fu Liang, Strained silicon device manufacturing method.
  89. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  90. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  91. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures with elevated source/drain regions.
  92. Langdo,Thomas A.; Currie,Matthew T.; Braithwaite,Glyn; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator finFET device structures.
  93. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  94. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  95. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  96. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  97. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  98. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman, Tri-gate devices and methods of fabrication.
  99. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  100. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  101. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  102. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  103. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  104. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  105. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  106. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  107. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  108. Chau,Robert; Datta,Suman; Doyle,Brian S; Jin,Been Yih, Tri-gate transistors and methods to fabricate same.
  109. Shaheen, Mohamad A.; Rachmady, Willy; Tolchinsky, Peter, Ultra-thin oxide bonding for S1 to S1 dual orientation bonding.
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