IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0595931
(2000-06-16)
|
우선권정보 |
JP-0173015 (1999-06-18); JP-0299700 (1999-10-21) |
발명자
/ 주소 |
- Nakazato, Ryu
- Maeda, Mayumi
|
출원인 / 주소 |
|
대리인 / 주소 |
Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
|
인용정보 |
피인용 횟수 :
16 인용 특허 :
9 |
초록
▼
The CPU operates at the highest speed in start processing of an operating system. When a power-saving driver receives a start completion message from the operating system, the power-saving driver waits for a predetermined period until user operation to a computer system is enabled, and then sets the
The CPU operates at the highest speed in start processing of an operating system. When a power-saving driver receives a start completion message from the operating system, the power-saving driver waits for a predetermined period until user operation to a computer system is enabled, and then sets the processing speed of the CPU to a user-designated speed. When the power-saving driver receives from the OS an OS termination start message representing the start of shutdown processing, the power-saving driver cancels setting of the user-designated speed, and returns the CPU to, e.g., the highest speed. Hence, start processing/shutdown processing can be executed at a high speed regardless of the set value of the user-designated speed.
대표청구항
▼
The CPU operates at the highest speed in start processing of an operating system. When a power-saving driver receives a start completion message from the operating system, the power-saving driver waits for a predetermined period until user operation to a computer system is enabled, and then sets the
The CPU operates at the highest speed in start processing of an operating system. When a power-saving driver receives a start completion message from the operating system, the power-saving driver waits for a predetermined period until user operation to a computer system is enabled, and then sets the processing speed of the CPU to a user-designated speed. When the power-saving driver receives from the OS an OS termination start message representing the start of shutdown processing, the power-saving driver cancels setting of the user-designated speed, and returns the CPU to, e.g., the highest speed. Hence, start processing/shutdown processing can be executed at a high speed regardless of the set value of the user-designated speed. that reconstructs the instruction execution stream based on the cache information, the sequenced instructions information and the instruction execution information. 12. The apparatus of claim 11, wherein the processor is an out-of-order speculative processor. 13. The apparatus of claim 11, wherein the sequenced instructions information is stored sequentially as the instructions are sequenced. 14. The apparatus of claim 11, wherein the storage device further stores updated cache information corresponding to instructions stored in the instruction cache when a cache load operation is performed. 15. The apparatus of claim 14, wherein the cache information and the updated cache information are stored sequentially along with the sequenced instructions information in the storage device. 16. The apparatus of claim 11, wherein the sequenced instructions information includes speculatively sequenced instructions information corresponding to a branch instruction. 17. The apparatus of claim 11, wherein the sequenced instructions information includes a unique identifier of a sequenced instruction. 18. The apparatus of claim 17, wherein the unique identifier is an index into a completion table, the index corresponding to the sequenced instruction. 19. The apparatus of claim 11, wherein the storage device is external to the processor. 20. The apparatus of claim 11, wherein the storage device is internal to the processor. 21. A computer program product in a computer readable medium for use with a processor for reconstructing an instruction execution stream of program instructions, comprising: first instructions for storing, in a storage device, cache information corresponding to instructions loaded in an instruction cache; second instructions for storing, in the storage device, sequenced instructions information corresponding to instructions sequenced for execution; third instructions for storing, in the storage device, instruction execution information corresponding to instructions executed by the processor; and fourth instructions for reconstructing the instruction execution stream based on the cache information, the sequenced instructions information and the instruction execution information. 22. The computer program product of claim 21, wherein the processor is an out-of-order speculative processor. 23. The computer program product of claim 21, wherein the sequenced instructions information is stored sequentially as the instructions are sequenced. 24. The computer program product of claim 21, further comprising fifth instructions for storing updated cache information corresponding to instructions stored in the instruction cache when a cache load operation is performed. 25. The computer program product of claim 24, wherein the cache, information and the updated cache information are stored sequentially along with the sequenced instructions information in the storage device. 26. The computer program product of claim 21, wherein sequenced instructions information includes speculatively sequenced instructions information corresponding to a branch instruction. 27. The computer program product of claim 21, wherein the sequenced instructions information includes a unique identifier of a sequenced instruction. 28. The computer program product of claim 27, wherein the unique identifier is an index into a completion table, the index corresponding to the sequenced instruction. 29. The computer program product of claim 21, wherein the storage device is external to the processor. 30. The computer program product of claim 21, wherein the storage device is internal to the processor. 31. A system for reconstructing an instruction execution stream of program instructions, comprising: a processor; an instruction cache, coupled to the processor, for storing instructions; a sequencing unit, coupled to the instruction cache, for sequencing instructions fetched from the instruction cache, for execution by the processor; a storage device that st
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