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Global planarization method and apparatus

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
출원번호 US-0840496 (2001-04-23)
발명자 / 주소
  • Blalock, Guy
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 1  인용 특허 : 55

초록

An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or "puck" disposed between the rigid plate and the pressing s

대표청구항

An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or "puck" disposed between the rigid plate and the pressing s

이 특허에 인용된 특허 (55)

  1. Choinski Edward J. (Wayland MA), Apparatus and method for temporarily sealing holes in printed circuit boards.
  2. Kishii Sadahiro (Kawasaki JPX) Arimoto Yoshihiro (Kawasaki JPX), Apparatus and method for uniformly polishing a wafer.
  3. Inselmann Jrgen (Lhne DEX), Apparatus for bonding textile sheet-like structures.
  4. Shendon Norman (San Carlos CA), Chemical mechanical polishing apparatus with improved carrier and method of use.
  5. Shimomura Mariko (Yokohama JPX) Miyashita Naoto (Yokohama JPX) Ohashi Hiroyuki (Kamakura JPX), Chemical-mechanical polishing (CMP) method for controlling polishing rate using ionized water, and CMP apparatus.
  6. Chen Lai-Juh (Hsin-Chu TWX), Chemical/mechanical polish (CMP) thickness monitor.
  7. Sandhu Gurtej S. (Boise ID) Yu Chang (Boise ID) Doan Trung T. (Boise ID) Tuttle Mark E. (Boise ID), Conductive contact plug and a method of forming a conductive contact plug in an integrated circuit using laser planariza.
  8. Bunch Jesse C. (Silver Spring MD), Cube press.
  9. Blalock Guy T. ; Stroupe Hugh E. ; Gordon Brian F., Deadhesion method and mechanism for wafer processing.
  10. Blalock, Guy T.; Stroupe, Hugh E.; Gordon, Brian F., Deadhesion method and mechanism for wafer processing.
  11. Prybyla Judith Ann ; Taylor Gary Newton, Device fabrication involving planarization.
  12. Weling Milind G. (San Jose CA) Bothra Subhas (San Jose CA) Gabriel Calvin T. (Cupertino CA), Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing.
  13. Blalock Guy, Global planarization method and apparatus.
  14. Blalock Guy, Global planarization method and apparatus.
  15. Allman Derryl D. J. (Colorado Springs CO) Fuchs Kenneth P. (Colorado Springs CO), Global planarization using SOG and CMP.
  16. Miyashita Akimi (Toride JPX) Fujii Mutsumasa (Ibaraki-ken JPX) Mishina Haruo (Ushiku JPX), Hot press with pressure vessels to uniformly distribute pressure to the work piece.
  17. Sandhu Gurtej S. (Boise ID) Yu Chris C. (Austin TX), IC chemical mechanical planarization process incorporating slurry temperature control.
  18. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
  19. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
  20. Yu Chris C. (Boise ID) Sandhu Gurtej S. (Boise ID) Doan Trung T. (Boise ID), Integrated circuit polishing method.
  21. Chou Richard Tien-Hua (Wilmington DE), Ionomers based on copolymers of ethylene with both mono-and dicarboxylic acids.
  22. Tuttle Mark E. (Boise ID) Doan Trung T. (Boise ID) Fox Angus C. (Boise ID) Sandhu Gurtej S. (Boise ID) Stroupe Hugh E. (Boise ID), Method and apparatus for improving planarity of chemical-mechanical planarization operations.
  23. Hamamura Fumio (Kanagawa JPX) Oka Yukio (Yamaguchi JPX), Method and apparatus for pressure sticking a thin film to a base plate.
  24. Reavill Joseph A. (Mira Loma CA) Arachi John M. (Riverside CA), Method and apparatus for vacuum lamination of flex circuits.
  25. Tsunoda Kazuyoshi (Yuki JPX) Tonoki Kenji (Yuki JPX) Yokono Haruki (Yuki JPX) Kono Hisao (Yuki JPX) Yokoyama Ryoji (Musashino JPX) Kobayashi Kazuo (Shimodate JPX), Method and device for manufacturing a laminated material.
  26. Blalock, Guy T.; Stroupe, Hugh E.; Carroll, Lynn J., Method for applying uniform pressurized film across wafer.
  27. Paranjpe Ajit P. (Plano TX), Method for planarization.
  28. Dawson Robert (Austin TX) Ponder Kenneth J. (Las Gatos CA), Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical pol.
  29. Kim Sung C. (Boise ID) Meikle Scott (Boise ID), Method for shaping features of a semiconductor structure using chemical mechanical planarization (CMP).
  30. Hayashi Yoshihiro (Tokyo JPX), Method of flattening the surface of a semiconductor device by polishing.
  31. Blalock Guy (Boise ID) Wald Phillip G. (Boise ID), Method of forming a stacked capacitor with striated electrode.
  32. J. Mike Brooks ; Jerrold L. King ; Kevin Schofield, Method of forming an integrated circuit device having cyanate ester buffer coat.
  33. Tola Jeffry (Morrison IL), Method of making diaphragm-type pressure transducers.
  34. Matsuda Tetsuo (Poughkeepsie NY) Okumura Katsuya (Poughkeepsie NY), Method of planarizing a semiconductor workpiece surface.
  35. Schwarzbauer Herbert (Munich DEX), Method of securing electronic components to a substrate.
  36. Lowrey Tyler A. (Boise ID) Doan Trung T. (Boise ID) Cathey David A. (Boise ID) Rolfson J. Brett (Boise ID), Method to form high aspect ratio supports (spacers) for field emission display using micro-saw technology.
  37. Doan Trung T. (Boise ID) Yu Chris C. (Boise ID), Multiple step method of chemical-mechanical polishing which minimizes dishing.
  38. Kudo Takanori (Sayama JPX) Masuda Seiya (Tokorozawa JPX) Kinoshita Yoshiaki (Tokyo JPX) Przybilla Klaus (Frankfurt DEX) Endo Natsumi (Kawagoe JPX) Suehiro Natsumi (Kawagoe JPX) Okazaki Hiroshi (Kawag, Pattern forming material including photoacid and photobase generators for large exposure latitude.
  39. Eugene P. Marsh, Planarization of non-planar surfaces in device fabrication.
  40. Marsh Eugene P., Planarization of non-planar surfaces in device fabrication.
  41. Doan Trung T. ; Blalock Guy T. ; Durcan Mark ; Meikle Scott G., Planarization process for semiconductor substrates.
  42. Stroupe Hugh (Boise ID) Sharan Sujit (Boise ID) Sandhu Gurtej S. (Boise ID), Polishing apparatus, a polishing wafer carrier apparatus, a replacable component for a particular polishing apparatus an.
  43. Katakabe Ichiro (Kanagawa-ken JPX) Miyashita Naoto (Kanagawa-ken JPX) Akiyama Tatsuo (Tokyo JPX), Polishing method and apparatus for detecting a polishing end point of a semiconductor wafer.
  44. Robinson Karl M. (Boise ID), Polishing pad and a method for making a polishing pad with covalently bonded particles.
  45. Talieh Homayoun (San Jose CA) Weldon David E. (Los Gatos CA), Polishing pad cluster for polishing a semiconductor wafer.
  46. Karlsrud Chris (Chandler AZ), Polishing pad conditioning.
  47. Winkle Mark Robert (Lansdale PA), Positive acting photoresist comprising a photoacid, a photobase and a film forming acid-hardening resin system.
  48. Namysl Edmond (1907 Frederick Placentia CA 92670), Printed circuit board laminating machine.
  49. Jacob Adir (23 Juniper La. Framingham MA 01701), Process for dry sterilization of medical devices and materials.
  50. Nagashima Naoki (Kanagawa JPX) Takahashi Hiroshi (Kanagawa JPX), Process for planarizing surface of a semiconductor device.
  51. Bose Amitava (Nashua NH) Garver Marion M. (Marlborough MA) Nasr Andre I. (Marlborough MA) Cooperman Steven S. (Southborough MA), Shallow trench isolation process for high aspect ratio trenches.
  52. Blalock Guy (Boise ID) Wald Phillip G. (Boise ID), Stacked capacitor construction.
  53. Iijima Nobuo (Kawasaki JPX) Hayashida Akihisa (Kawasaki JPX), Tape-on-wafer mounting apparatus and method.
  54. Pasch Nicholas F. (Pacifica CA) Mallon Thomas G. (Santa Clara CA) Franklin Mark A. (Scott\s Valley CA), Techniques for assembling polishing pads for chemi-mechanical polishing of silicon wafers.
  55. Clover Richmond B. (1199 W. Vanderbilt Ct. Sunnyvale CA 94087), Vertically stacked planarization machine.

이 특허를 인용한 특허 (1)

  1. McCutcheon, Jeremy; Lamb, III, James E., Automated process and apparatus for planarization of topographical surfaces.
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