Metal-semiconductor diode clamped complementary field effect transistor integrated circuits
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/76
H01L-027/095
출원번호
US-0645366
(2000-08-24)
발명자
/ 주소
O, Kenneth K.
Huang, Feng-Jung
대리인 / 주소
Saliwanchik, Lloyd & Saliwanchik
인용정보
피인용 횟수 :
14인용 특허 :
10
초록▼
The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect
The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. This can allow the spacing between n- and p-type transistors to be reduced, thus reducing the area of the circuit. The subject invention can also allow the elimination of a metal contact by utilizing the metal layer used to form the metal-semiconductor junction in a complementary IGFET structure, to further reduce the circuit area. The subject invention is applicable to complementary metal oxide silicon (CMOS) devices. Advantageously, the manufacturing process required to produce the subject devices can require minimal adjustments to the standard processing steps used in conventional CMOS processing.
대표청구항▼
The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect
The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. This can allow the spacing between n- and p-type transistors to be reduced, thus reducing the area of the circuit. The subject invention can also allow the elimination of a metal contact by utilizing the metal layer used to form the metal-semiconductor junction in a complementary IGFET structure, to further reduce the circuit area. The subject invention is applicable to complementary metal oxide silicon (CMOS) devices. Advantageously, the manufacturing process required to produce the subject devices can require minimal adjustments to the standard processing steps used in conventional CMOS processing. gnetic insulator is selected from the group consisting of ferrites and perovskite ferromagnetic oxides. 11. The device of claim 1, further including a first sensor coupled to a first edge of said conductive film layer. 12. The device of claim 1, further including a first sensor coupled to a first edge of said conductive film layer, and a second sensor coupled to a second edge of the conductive film layer, opposite to the first edge, such that the electrical signal is a voltage generated substantially along an axis joining the first and second sensors. 13. The device of claim 1, further including an insulating layer disposed between said electrically-conductive layer and said ferromagnetic multilayer. 14. The device of claim 1, wherein said device is a field effect transistor (FET) in which said electrically-conductive layer is a conducting channel. 15. The device of claim 2, wherein said magnetic insulator is a magnetic oxide eontaining FeO, Fe2O3,Fe3O4,and mixtures thereof. 16. The device of claim 2, wherein said magnetic insulator has a coercivity of up to about 100 Oe. 17. The device of claim 1, further including a buffer layer; wherein said buffer layer is in contact with said ferromagnetic multilayer. 18. The device of claim 1, wherein said ferromagnetic multilayer has a top surface in an anisotropic shape. 19. The device of claim 18, wherein said anisotropic shape is an ellipse or a rectangle with an aspect ratio of at least about 3; wherein said aspect ratio is defined as the ratio of the length to the width. 20. The device of claim 1, further including a write line for configuring the magnetization orientation in the ferromagnetic layer. 21. The device of claim 1, wherein the ferromagnetic multilayer is coupled to a magnetic field generated by magnetically recorded data, the electrical signal generated is related to a value of the data, and the device operates as a magnetic field sensor. 22. The device of claim 12, wherein the ferromagnetic multilayer has an easy magnetization axis that is substantially parallel to the electrical current and substantially perpendicular to the axis joining the first and second sensors. 23. A memory device comprising: a conductive film layer having a top surface; a ferromagnetic multilayer having at least two configurable and stable magnetization orientation states corresponding to two different values of a data item stored in said device, and covering a portion of the top surface such that a fringe magnetic field having two states and configured substantially normal to the top s urface can be generated by an edge portion of the ferromagnetic layer; wherein two different electrical signals, each corresponding to a different one of the two different data values, can be generated in response to the two fringe magnetization field states acting on an electrical current flowing in the conductive film layer; and wherein the ferromagnetic multilayer comprises at least a first magnetic layer and a second magnetic layer. 24. The device of claim 23, further including a first sensor coupled to a first edge of the conductive film layer, and a second sensor coupled to a second edge of the conductive film layer, opposite to the first edge, such that the two different electrical signals are voltages generated substantially along an axis joining the first and second sensors. 25. The device of claim 24, wherein the two electrical signals comprise a first voltage output signal when a first value of the data item is stored in said device, and a second voltage output value when a second value of the data item is stored in said device. 26. A logic device for implementing a logic function relating a combination of one or more input signals to an output signal comprising: a conductive film layer having a top surface; a ferromagnetic multilayer having at least two stable magnetization orientation states and covering a portion of the top surface s uch that a fringe magnetic field can be generated substantially normal to the top surface by an edge portion of the ferromagnetic layer; and a write line for inductively coupling! the ferromagnetic layer with a magnetic field generated by said input data signals on the wire, the input data signals having one of a first and a second current value, an electrical output signal generated in response to the fringe magnetic field acting on an electrical current flowing in the conductive film layer, and wherein the electrical output signal relates to said input signals and to said logic function; and wherein the ferromagnetic multilayer comprises at least a first magnetic layer and a second magnetic layer. 27. The device of claim 26, wherein the electrical output signal has a first value when the ferromagnetic multilayer magnetization orientation state is altered by magnetic fields corresponding to a first combination of said input data signals related to said logic function, and the electrical ouput signal has a second value when the ferromagnetic multilayer magnetization state is not altered by magnetic fields corresponding to a second combination of said input data signals. 28. The device of claim 26, wherein the magnetization orientation state of the ferromagnetic multilayer corresponds to a result of said logic function implemented in said device, and this result is stored in said device until the magnetization orientation state is altered by a subsequent combination of input signals. 29. The device of claim 28, wherein the magnetization state of the ferromagnetic layer can be set initially based on the logical function to be implemented by said device. 30. An electronic device comprising: a field effect transistor (FET), including a source region, a drain region, a gate and a channel; a ferromagnetic multi layer having a configurable magnetization orientation, and positioned relative to the gate and channel such that a fringe magnetic field directed substantially normal to the channel can be generated by an edge portion of the ferromagnetic multilayer; wherein an electrical signal related to the magnetization orientation of the ferromagnetic multilayer can be generated in response to the fringe magnetic field acting on an electrical current flowing between the source and drain of the FET; and wherein the ferromagnetic multilayer comprises at least a first magnetic layer and a second magnetic layer. 31. The device of claim 30, wherein the electrical current flows between a first bias terminal coupled to the source of the FET and a second bias terminal coupled to the drain of the FET. 32. A memory device comprising: a field effect transistor (FET), including a source, a drain, a gate and a channel; a ferromagnetic multilayer having at least two configurable and stable magnetization orientation states corresponding to two different values of a data item stored in said device, and positioned relative to the gate and channel such that a fringe magnetic field directed substantially normal to the channel can be generated by an edge portion of the ferromagnetic multilayer; wherein two different output electrical signals corresponding to the two different data values can be generated in response to the fringe magnetization field acting on an electrical current flowing in the channel; and wherein the ferromagnetic multilayer comprises at least a first magnetic layer and a second magnetic layer.
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